[llvm] [AMDGPU][GlobalISel] Assign bank to vregs created by RegBankCombiner (PR #216270)

[Arseniy Obolenskiy via llvm-commits]

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@@ -0,0 +1,71 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
+
+# same_val_zero (xor x, x -> 0) creates a vreg with no bank after RegBankSelect.
+
+---
+name: xor_same_val_v2s16
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; CHECK-LABEL: name: xor_same_val_v2s16
+    ; CHECK: liveins: $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_CONSTANT i16 0
+    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR]](<2 x s16>)
+    ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](<2 x s16>)
+    %0:sgpr(<2 x s16>) = COPY $sgpr0
+    %1:vgpr(<2 x s16>) = COPY %0(<2 x s16>)
+    %2:vgpr(<2 x s16>) = COPY %0(<2 x s16>)
+    %3:vgpr(<2 x s16>) = G_XOR %1, %2
+    $vgpr0 = COPY %3(<2 x s16>)
+...
+---
+name: xor_same_val_s32
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: xor_same_val_s32
+    ; CHECK: liveins: $vgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
+    ; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = G_XOR %0, %0
+    $vgpr0 = COPY %1(s32)
+...
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aobolensk wrote:

Added LLVM IR input

https://github.com/llvm/llvm-project/pull/216270