[llvm] 770ea2e - RISCV: Pass MachineRegisterInfo to isVLKnownLE (#219402)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 28 02:37:58 PDT 2026
Author: Matt Arsenault
Date: 2026-08-28T11:37:53+02:00
New Revision: 770ea2efd2fa1a0de6fe8ea741d536ea0ee2b2c6
URL: https://github.com/llvm/llvm-project/commit/770ea2efd2fa1a0de6fe8ea741d536ea0ee2b2c6
DIFF: https://github.com/llvm/llvm-project/commit/770ea2efd2fa1a0de6fe8ea741d536ea0ee2b2c6.diff
LOG: RISCV: Pass MachineRegisterInfo to isVLKnownLE (#219402)
isVLKnownLE and its getEffectiveImm helper used the VL operands to reach
the MachineRegisterInfo. Pass it directly so they no longer depend on
MachineOperand::getParent().
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 11544650bbe74..ee47963aa041e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -5330,12 +5330,12 @@ unsigned RISCV::getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW) {
return Scaled;
}
-static std::optional<int64_t> getEffectiveImm(const MachineOperand &MO) {
+static std::optional<int64_t> getEffectiveImm(const MachineRegisterInfo &MRI,
+ const MachineOperand &MO) {
assert(MO.isImm() || MO.getReg().isVirtual());
if (MO.isImm())
return MO.getImm();
- const MachineInstr *Def =
- MO.getParent()->getMF()->getRegInfo().getVRegDef(MO.getReg());
+ const MachineInstr *Def = MRI.getVRegDef(MO.getReg());
int64_t Imm;
if (isLoadImm(Def, Imm))
return Imm;
@@ -5343,9 +5343,9 @@ static std::optional<int64_t> getEffectiveImm(const MachineOperand &MO) {
}
/// Given two VL operands, do we know that LHS <= RHS? Must be used in SSA form.
-bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
- assert((LHS.isImm() || LHS.getParent()->getMF()->getRegInfo().isSSA()) &&
- (RHS.isImm() || RHS.getParent()->getMF()->getRegInfo().isSSA()));
+bool RISCV::isVLKnownLE(const MachineRegisterInfo &MRI,
+ const MachineOperand &LHS, const MachineOperand &RHS) {
+ assert((LHS.isImm() || MRI.isSSA()) && (RHS.isImm() || MRI.isSSA()));
if (LHS.isReg() && RHS.isReg() && LHS.getReg().isVirtual() &&
LHS.getReg() == RHS.getReg())
return true;
@@ -5355,8 +5355,8 @@ bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
return true;
if (LHS.isImm() && LHS.getImm() == RISCV::VLMaxSentinel)
return false;
- std::optional<int64_t> LHSImm = getEffectiveImm(LHS),
- RHSImm = getEffectiveImm(RHS);
+ std::optional<int64_t> LHSImm = getEffectiveImm(MRI, LHS),
+ RHSImm = getEffectiveImm(MRI, RHS);
if (!LHSImm || !RHSImm)
return false;
return LHSImm <= RHSImm;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index c75335ba7d145..559f6f4cb6069 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -410,7 +410,8 @@ unsigned getDestLog2EEW(const MCInstrDesc &Desc, unsigned Log2SEW);
static constexpr int64_t VLMaxSentinel = -1LL;
/// Given two VL operands, do we know that LHS <= RHS?
-bool isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS);
+bool isVLKnownLE(const MachineRegisterInfo &MRI, const MachineOperand &LHS,
+ const MachineOperand &RHS);
// Mask assignments for floating-point
static constexpr unsigned FPMASK_Negative_Infinity = 0x001;
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index a9eb20f32d9db..7f39253a63068 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -54,10 +54,10 @@ struct DemandedVL {
return !VL.isIdenticalTo(Other.VL);
}
- DemandedVL max(const DemandedVL &X) const {
- if (RISCV::isVLKnownLE(VL, X.VL))
+ DemandedVL max(const MachineRegisterInfo &MRI, const DemandedVL &X) const {
+ if (RISCV::isVLKnownLE(MRI, VL, X.VL))
return X;
- if (RISCV::isVLKnownLE(X.VL, VL))
+ if (RISCV::isVLKnownLE(MRI, X.VL, VL))
return *this;
return DemandedVL::vlmax();
}
@@ -1089,7 +1089,7 @@ RISCVVLOptimizerImpl::getMinimumVLForUser(const MachineOperand &UserOp) const {
if (UserOp.isTied()) {
assert(UserOp.getOperandNo() == UserMI.getNumExplicitDefs() &&
RISCVII::isFirstDefTiedToFirstUse(UserMI.getDesc()));
- if (!RISCV::isVLKnownLE(DemandedVLs.lookup(&UserMI).VL, VLOp)) {
+ if (!RISCV::isVLKnownLE(*MRI, DemandedVLs.lookup(&UserMI).VL, VLOp)) {
LLVM_DEBUG(dbgs() << " Abort because user is passthru in "
"instruction with demanded tail\n");
return DemandedVL::vlmax();
@@ -1105,7 +1105,7 @@ RISCVVLOptimizerImpl::getMinimumVLForUser(const MachineOperand &UserOp) const {
// If we know the demanded VL of UserMI, then we can reduce the VL it
// requires.
- if (RISCV::isVLKnownLE(DemandedVLs.lookup(&UserMI).VL, VLOp))
+ if (RISCV::isVLKnownLE(*MRI, DemandedVLs.lookup(&UserMI).VL, VLOp))
return DemandedVLs.lookup(&UserMI);
return VLOp;
@@ -1253,7 +1253,7 @@ bool RISCVVLOptimizerImpl::tryReduceVL(MachineInstr &MI,
CommonVL = VLMI->getOperand(RISCVII::getVLOpNum(VLMI->getDesc()));
}
- if (!RISCV::isVLKnownLE(CommonVL, VLOp)) {
+ if (!RISCV::isVLKnownLE(*MRI, CommonVL, VLOp)) {
LLVM_DEBUG(dbgs() << " Abort due to CommonVL not <= VLOp.\n");
return false;
}
@@ -1315,7 +1315,7 @@ void RISCVVLOptimizerImpl::transfer(const MachineInstr &MI) {
for (const MachineOperand &MO : virtual_vec_uses(MI)) {
const MachineInstr *Def = MRI->getVRegDef(MO.getReg());
DemandedVL Prev = DemandedVLs[Def];
- DemandedVLs[Def] = DemandedVLs[Def].max(getMinimumVLForUser(MO));
+ DemandedVLs[Def] = DemandedVLs[Def].max(*MRI, getMinimumVLForUser(MO));
if (DemandedVLs[Def] != Prev)
Worklist.insert(Def);
}
diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
index 2c09bdb6937d4..0f2703907a717 100644
--- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp
@@ -363,7 +363,7 @@ bool RISCVVectorPeepholeImpl::convertSameMaskVMergeToVMv(MachineInstr &MI) {
const MachineOperand &TrueVL =
True->getOperand(RISCVII::getVLOpNum(True->getDesc()));
Register FalseReg = MI.getOperand(2).getReg();
- if (!RISCV::isVLKnownLE(MIVL, TrueVL)) {
+ if (!RISCV::isVLKnownLE(*MRI, MIVL, TrueVL)) {
Register PassthruReg = MI.getOperand(1).getReg();
if (FalseReg.isValid() && FalseReg != PassthruReg)
return false;
@@ -530,7 +530,7 @@ bool RISCVVectorPeepholeImpl::foldUndefPassthruVMV_V_V(MachineInstr &MI) {
MachineOperand &SrcPolicy =
Src->getOperand(RISCVII::getVecPolicyOpNum(Src->getDesc()));
- if (RISCV::isVLKnownLE(MIVL, SrcVL))
+ if (RISCV::isVLKnownLE(*MRI, MIVL, SrcVL))
SrcPolicy.setImm(SrcPolicy.getImm() | RISCVVType::TAIL_AGNOSTIC);
}
@@ -594,7 +594,7 @@ bool RISCVVectorPeepholeImpl::foldVMV_V_V(MachineInstr &MI) {
// so we don't need to handle a smaller source VL here. However, the
// user's VL may be larger
MachineOperand &SrcVL = Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
- if (!RISCV::isVLKnownLE(SrcVL, MI.getOperand(3)))
+ if (!RISCV::isVLKnownLE(*MRI, SrcVL, MI.getOperand(3)))
return false;
// If the new passthru doesn't dominate Src, try to move Src so it does.
@@ -621,7 +621,7 @@ bool RISCVVectorPeepholeImpl::foldVMV_V_V(MachineInstr &MI) {
// If MI was tail agnostic and the VL didn't increase, preserve it.
int64_t Policy = RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED;
if ((MI.getOperand(5).getImm() & RISCVVType::TAIL_AGNOSTIC) &&
- RISCV::isVLKnownLE(MI.getOperand(3), SrcVL))
+ RISCV::isVLKnownLE(*MRI, MI.getOperand(3), SrcVL))
Policy |= RISCVVType::TAIL_AGNOSTIC;
Src->getOperand(RISCVII::getVecPolicyOpNum(Src->getDesc())).setImm(Policy);
}
@@ -721,9 +721,9 @@ bool RISCVVectorPeepholeImpl::foldVMergeToMask(MachineInstr &MI) const {
True.getOperand(RISCVII::getVLOpNum(True.getDesc()));
MachineOperand MinVL = MachineOperand::CreateImm(0);
- if (RISCV::isVLKnownLE(TrueVL, VMergeVL))
+ if (RISCV::isVLKnownLE(*MRI, TrueVL, VMergeVL))
MinVL = TrueVL;
- else if (RISCV::isVLKnownLE(VMergeVL, TrueVL))
+ else if (RISCV::isVLKnownLE(*MRI, VMergeVL, TrueVL))
MinVL = VMergeVL;
else if (!TruePassthru && !True.mayLoadOrStore())
// If True's passthru is undef, we can use vmerge's vl.
@@ -746,7 +746,7 @@ bool RISCVVectorPeepholeImpl::foldVMergeToMask(MachineInstr &MI) const {
// to the tail. In that case we always need to use tail undisturbed to
// preserve them.
uint64_t Policy = RISCVVType::TAIL_UNDISTURBED_MASK_UNDISTURBED;
- if (!PassthruReg && RISCV::isVLKnownLE(VMergeVL, MinVL))
+ if (!PassthruReg && RISCV::isVLKnownLE(*MRI, VMergeVL, MinVL))
Policy |= RISCVVType::TAIL_AGNOSTIC;
assert(RISCVII::hasVecPolicyOp(True.getDesc().TSFlags) &&
@@ -869,7 +869,7 @@ bool RISCVVectorPeepholeImpl::foldVMANDToMaskedCompare(MachineInstr &MI) const {
Cmp.getOperand(RISCVII::getVLOpNum(Cmp.getDesc()));
const MachineOperand &MIVL =
MI.getOperand(RISCVII::getVLOpNum(MI.getDesc()));
- if (!RISCV::isVLKnownLE(MIVL, CmpVL))
+ if (!RISCV::isVLKnownLE(*MRI, MIVL, CmpVL))
continue;
const MachineOperand &MaskOp = MI.getOperand(MaskIdx);
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