[llvm] RISCV: Pass MachineRegisterInfo to isVLKnownLE (PR #219402)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> Is this needed for the MIR block arguments work? I'm not fundamentally opposed to plumbing it through manually but I intentionally fetched the MRI from the parent to avoid this in [633233c](https://github.com/llvm/llvm-project/commit/633233c04cfa2a342cceaa0b4833fb35d61c3900)

No, this is another aspirational refactor I want to do, which is to eliminate the parent from MachineOperand. This is an incredible waste of memory, it's 8 bytes per very large number of operands and never necessary 

https://github.com/llvm/llvm-project/pull/219402