[llvm] [AMDGPU] Fix uniform fcopysign pattern (PR #218644)

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Shoreshen wrote:

> Regarding the DetectDeadlanes, if I understand correctly the problem is the mix of vgpr_32 and vgpr_16? The lane mask of vpgr16 is 1, while for vgpr32 subreg lane mask, lo16 is 2 and hi16 is 1. The order of lo16 and hi16 are reverted. My understanding is that this is causing no overlap between lo16 and vgpr16 lane mask and the DetectDeadlane think the inst is dead.
> 
> As I mentioned above that I am working on a patch in isel trying to legalize this sreg32/vgpr16 issue but it's not yet ready. For now I have two thoughts:
> 
> 1. In isel pattern, we can replace reg_sequence with "v_cvt_u32_u16". This will take care of the reg size issue between divergent and uniform input, but it's bad as it generates more insts
> 2. Fix this issue in si-fix-sgpr-copy pass. From the MIR flow,
> 
> ```
> bb.2.positive:
> ; predecessors: %bb.1
>   successors: %bb.4(0x80000000); %bb.4(100.00%)
> 
>   %33:vgpr_16 = nofpexcept V_ADD_F16_t16_e64 0, %0:sreg_32, 0, %0:sreg_32, 0, 0, 0, implicit $mode, implicit $exec
>   %3:sreg_32 = COPY %33:vgpr_16
>   S_BRANCH %bb.4
> ...
> bb.4.exit:
>   %5:sreg_32 = PHI %1:sreg_32, %bb.1, %3:sreg_32, %bb.2
> ```
> 
> I think these are moved to VALU in si-fix-sgpr-copy pass? The `%3:sreg_32 = COPY %33:vgpr_16` is legalized to a `reg_sequence`, but the following user legalization starting from `phi` node is not done properly.

I think the problem is like `%37:vgpr_32 = REG_SEQUENCE %53:vgpr_32, %subreg.lo16, %38:sreg_32, %subreg.hi16` we lost the semantic of which half of `%53:vgpr_32` is copying to the `lo16`.

It can be either of the following two:
```
%37:vgpr_32 = REG_SEQUENCE %53:vgpr_32.lo16, %subreg.lo16, %38:sreg_32, %subreg.hi16
%37:vgpr_32 = REG_SEQUENCE %53:vgpr_32.hi16, %subreg.lo16, %38:sreg_32, %subreg.hi16
```

So without correct semantic, the behavior of detect-deat-lane pass should not be blamed....

https://github.com/llvm/llvm-project/pull/218644