[llvm] 57f293f - [X86] Emit adox instead of adc for overflow add (#216609)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 27 22:12:45 PDT 2026
Author: AZero13
Date: 2026-08-27T22:12:40-07:00
New Revision: 57f293f1803413d254e9970cc343cc74b6752fc1
URL: https://github.com/llvm/llvm-project/commit/57f293f1803413d254e9970cc343cc74b6752fc1
DIFF: https://github.com/llvm/llvm-project/commit/57f293f1803413d254e9970cc343cc74b6752fc1.diff
LOG: [X86] Emit adox instead of adc for overflow add (#216609)
ADOX is like ADC but with OF instead of the CF and can only be encoded
with a pair of 32 or 64 bit regs.
Basically this applies in cases where the overflow flag is being added.
Added:
llvm/test/CodeGen/X86/adox-flags.ll
llvm/test/CodeGen/X86/adox.ll
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86InstrArithmetic.td
llvm/lib/Target/X86/X86InstrFragments.td
llvm/lib/Target/X86/X86InstrPredicates.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a37012133e431..c8a38aa1bb154 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -53569,6 +53569,21 @@ static SDValue combineAddOrSubToADCOrSBB(bool IsSub, const SDLoc &DL, EVT VT,
DAG.getVTList(VT, MVT::i32), X,
DAG.getConstant(0, DL, VT), EFLAGS);
}
+ if (!IsSub && CC == X86::COND_O &&
+ (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32 || VT == MVT::i64) &&
+ DAG.getSubtarget<X86Subtarget>().hasADX()) {
+ // X + (overflow_from_OF ? 1 : 0) --> adox X, 0
+ // NOTE: For i8/i16, ADOX32's OF output does not match the original iN
+ // overflow. This is safe because this ADOX replaces an ISD::ADD, so its OF
+ // output is natively dead. Its ANY_EXTEND operands ensure future transforms
+ // cannot mathematically prove the OF output is useful, preventing misuse.
+ EVT AdoxVT = (VT == MVT::i8 || VT == MVT::i16) ? MVT::i32 : VT;
+ SDValue AdoxX = DAG.getAnyExtOrTrunc(X, DL, AdoxVT);
+ SDValue Adox =
+ DAG.getNode(X86ISD::ADOX, DL, DAG.getVTList(AdoxVT, MVT::i32), AdoxX,
+ DAG.getConstant(0, DL, AdoxVT), EFLAGS);
+ return DAG.getAnyExtOrTrunc(Adox, DL, VT);
+ }
if (ZeroSecondOpOnly)
return SDValue();
@@ -59817,6 +59832,57 @@ static SDValue combineADC(SDNode *N, SelectionDAG &DAG,
return SDValue();
}
+// Optimize RES, EFLAGS = X86ISD::ADOX LHS, RHS, EFLAGS
+static SDValue combineADOX(SDNode *N, SelectionDAG &DAG) {
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ SDValue CarryIn = N->getOperand(2);
+ auto *LHSC = dyn_cast<ConstantSDNode>(LHS);
+ auto *RHSC = dyn_cast<ConstantSDNode>(RHS);
+
+ // Canonicalize constant to RHS.
+ if (LHSC && !RHSC)
+ return DAG.getNode(X86ISD::ADOX, SDLoc(N), N->getVTList(), RHS, LHS,
+ CarryIn);
+
+ // Fold ADOX(ADD(X,Y),0,Carry) -> ADOX(X,Y,Carry)
+ // ISD::ADD produces no EFLAGS, so we only need to ensure the ADOX's own
+ // flag output is not needed before replacing it with a 2-operand ADOX.
+ SDValue AddOp = LHS;
+
+ // Unwrap extensions. This changes what the wide intermediate represents,
+ // but we will verify later that all uses of the wide result are
+ // truncations to the original width.
+ if (AddOp.getOpcode() == ISD::ANY_EXTEND ||
+ AddOp.getOpcode() == ISD::ZERO_EXTEND)
+ AddOp = AddOp.getOperand(0);
+
+ if (AddOp.getOpcode() == ISD::ADD && RHSC && RHSC->isZero() &&
+ !needCarryOrOverflowFlag(SDValue(N, 1))) {
+ if (AddOp != LHS) {
+ unsigned OrigBits = AddOp.getValueSizeInBits();
+ for (SDUse &Use : N->uses()) {
+ if (Use.getResNo() == 0) {
+ SDNode *User = Use.getUser();
+ if (User->getOpcode() != ISD::TRUNCATE ||
+ User->getValueSizeInBits(0) > OrigBits)
+ return SDValue();
+ }
+ }
+ }
+
+ SDValue X = AddOp.getOperand(0);
+ SDValue Y = AddOp.getOperand(1);
+ if (AddOp != LHS) {
+ X = DAG.getNode(LHS.getOpcode(), SDLoc(N), LHS.getValueType(), X);
+ Y = DAG.getNode(LHS.getOpcode(), SDLoc(N), LHS.getValueType(), Y);
+ }
+ return DAG.getNode(X86ISD::ADOX, SDLoc(N), N->getVTList(), X, Y, CarryIn);
+ }
+
+ return SDValue();
+}
+
static SDValue matchPMADDWD(SelectionDAG &DAG, SDNode *N,
const SDLoc &DL, EVT VT,
const X86Subtarget &Subtarget) {
@@ -63511,6 +63577,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
case X86ISD::CLOAD:
case X86ISD::CSTORE: return combineX86CloadCstore(N, DAG);
case X86ISD::SBB: return combineSBB(N, DAG);
+ case X86ISD::ADOX: return combineADOX(N, DAG);
case X86ISD::ADC: return combineADC(N, DAG, DCI);
case ISD::MUL: return combineMul(N, DAG, DCI, Subtarget);
case ISD::UDIV:
diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td
index c91600525d1eb..d3793381e6caa 100644
--- a/llvm/lib/Target/X86/X86InstrArithmetic.td
+++ b/llvm/lib/Target/X86/X86InstrArithmetic.td
@@ -1459,7 +1459,7 @@ let Uses = [RDX] in
//===----------------------------------------------------------------------===//
// ADCX and ADOX Instructions
//
-// We don't have patterns for these as there is no advantage over ADC for
+// We don't have patterns for ADCX as there is no advantage over ADC for
// most code.
let Form = MRMSrcReg in {
def ADCX32rr : BinOpRRF_RF<0xF6, "adcx", Xi32>, T8, PD;
@@ -1493,3 +1493,34 @@ let Form = MRMSrcMem in {
def ADOX64rm_ND : BinOpRMF_RF<0x66, "adox", Xi64, null_frag, 1>, XS;
}
}
+
+// ADOX patterns
+let Predicates = [HasADX, HasNDD] in {
+ def : Pat<(X86adox_flag GR32:$src1, GR32:$src2, EFLAGS),
+ (ADOX32rr_ND GR32:$src1, GR32:$src2)>;
+ def : Pat<(X86adox_flag GR64:$src1, GR64:$src2, EFLAGS),
+ (ADOX64rr_ND GR64:$src1, GR64:$src2)>;
+ def : Pat<(X86adox_flag GR32:$src1, (loadi32 addr:$src2), EFLAGS),
+ (ADOX32rm_ND GR32:$src1, addr:$src2)>;
+ def : Pat<(X86adox_flag GR64:$src1, (loadi64 addr:$src2), EFLAGS),
+ (ADOX64rm_ND GR64:$src1, addr:$src2)>;
+ def : Pat<(X86adox_flag (loadi32 addr:$src2), GR32:$src1, EFLAGS),
+ (ADOX32rm_ND GR32:$src1, addr:$src2)>;
+ def : Pat<(X86adox_flag (loadi64 addr:$src2), GR64:$src1, EFLAGS),
+ (ADOX64rm_ND GR64:$src1, addr:$src2)>;
+}
+
+let Predicates = [HasADX, NoNDD] in {
+ def : Pat<(X86adox_flag GR32:$src1, GR32:$src2, EFLAGS),
+ (ADOX32rr GR32:$src1, GR32:$src2)>;
+ def : Pat<(X86adox_flag GR64:$src1, GR64:$src2, EFLAGS),
+ (ADOX64rr GR64:$src1, GR64:$src2)>;
+ def : Pat<(X86adox_flag GR32:$src1, (loadi32 addr:$src2), EFLAGS),
+ (ADOX32rm GR32:$src1, addr:$src2)>;
+ def : Pat<(X86adox_flag GR64:$src1, (loadi64 addr:$src2), EFLAGS),
+ (ADOX64rm GR64:$src1, addr:$src2)>;
+ def : Pat<(X86adox_flag (loadi32 addr:$src2), GR32:$src1, EFLAGS),
+ (ADOX32rm GR32:$src1, addr:$src2)>;
+ def : Pat<(X86adox_flag (loadi64 addr:$src2), GR64:$src1, EFLAGS),
+ (ADOX64rm GR64:$src1, addr:$src2)>;
+}
diff --git a/llvm/lib/Target/X86/X86InstrFragments.td b/llvm/lib/Target/X86/X86InstrFragments.td
index a9910dfedbfcc..43a07e5971952 100644
--- a/llvm/lib/Target/X86/X86InstrFragments.td
+++ b/llvm/lib/Target/X86/X86InstrFragments.td
@@ -390,6 +390,7 @@ def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags,
def X86umul_flag : SDNode<"X86ISD::UMUL", SDTBinaryArithWithFlags,
[SDNPCommutative]>;
def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>;
+def X86adox_flag : SDNode<"X86ISD::ADOX", SDTBinaryArithWithFlagsInOut>;
def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>;
def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags,
diff --git a/llvm/lib/Target/X86/X86InstrPredicates.td b/llvm/lib/Target/X86/X86InstrPredicates.td
index fd03fa24a18c8..1b177db55d276 100644
--- a/llvm/lib/Target/X86/X86InstrPredicates.td
+++ b/llvm/lib/Target/X86/X86InstrPredicates.td
@@ -193,6 +193,7 @@ def HasAMXAVX512 : Predicate<"Subtarget->hasAMXAVX512()">;
def HasUINTR : Predicate<"Subtarget->hasUINTR()">;
def HasUSERMSR : Predicate<"Subtarget->hasUSERMSR()">;
def HasCRC32 : Predicate<"Subtarget->hasCRC32()">;
+def HasADX : Predicate<"Subtarget->hasADX()">;
def HasX86_64 : Predicate<"Subtarget->hasX86_64()">;
def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
diff --git a/llvm/test/CodeGen/X86/adox-flags.ll b/llvm/test/CodeGen/X86/adox-flags.ll
new file mode 100644
index 0000000000000..718156a42267f
--- /dev/null
+++ b/llvm/test/CodeGen/X86/adox-flags.ll
@@ -0,0 +1,137 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+adx,+ndd | FileCheck %s --check-prefixes=CHECK,NDD
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+adx | FileCheck %s --check-prefixes=CHECK,ADX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-adx | FileCheck %s --check-prefixes=CHECK,NOADX
+
+declare { i8, i1 } @llvm.sadd.with.overflow.i8(i8, i8)
+
+define i32 @adox_test_flags(i32 %a, i32 %b, i8 %c, i8 %d) {
+; NDD-LABEL: adox_test_flags:
+; NDD: # %bb.0:
+; NDD-NEXT: addb %cl, %dl, %al
+; NDD-NEXT: adoxl %esi, %edi, %eax
+; NDD-NEXT: testl %eax, %eax
+; NDD-NEXT: movl $10, %ecx
+; NDD-NEXT: cmovel %ecx, %eax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_flags:
+; ADX: # %bb.0:
+; ADX-NEXT: addb %cl, %dl
+; ADX-NEXT: adoxl %esi, %edi
+; ADX-NEXT: testl %edi, %edi
+; ADX-NEXT: movl $10, %eax
+; ADX-NEXT: cmovnel %edi, %eax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_flags:
+; NOADX: # %bb.0:
+; NOADX-NEXT: # kill: def $esi killed $esi def $rsi
+; NOADX-NEXT: # kill: def $edi killed $edi def $rdi
+; NOADX-NEXT: xorl %r8d, %r8d
+; NOADX-NEXT: addb %cl, %dl
+; NOADX-NEXT: seto %r8b
+; NOADX-NEXT: leal (%rdi,%rsi), %eax
+; NOADX-NEXT: addl %eax, %r8d
+; NOADX-NEXT: movl $10, %eax
+; NOADX-NEXT: cmovnel %r8d, %eax
+; NOADX-NEXT: retq
+ %ssub = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i32
+ %sum = add i32 %a, %b
+ %res = add i32 %sum, %ov.ext
+ %cmp = icmp eq i32 %res, 0
+ %sel = select i1 %cmp, i32 10, i32 %res
+ ret i32 %sel
+}
+
+define i8 @adox_test_flags_i8(i8 %a, i8 %b, i8 %c, i8 %d) {
+; NDD-LABEL: adox_test_flags_i8:
+; NDD: # %bb.0:
+; NDD-NEXT: addb %cl, %dl, %al
+; NDD-NEXT: adoxl %esi, %edi, %eax
+; NDD-NEXT: testb %al, %al
+; NDD-NEXT: movl $10, %ecx
+; NDD-NEXT: cmovel %ecx, %eax
+; NDD-NEXT: # kill: def $al killed $al killed $eax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_flags_i8:
+; ADX: # %bb.0:
+; ADX-NEXT: addb %cl, %dl
+; ADX-NEXT: adoxl %esi, %edi
+; ADX-NEXT: testb %dil, %dil
+; ADX-NEXT: movl $10, %eax
+; ADX-NEXT: cmovnel %edi, %eax
+; ADX-NEXT: # kill: def $al killed $al killed $eax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_flags_i8:
+; NOADX: # %bb.0:
+; NOADX-NEXT: addb %cl, %dl
+; NOADX-NEXT: seto %al
+; NOADX-NEXT: addb %sil, %dil
+; NOADX-NEXT: addb %al, %dil
+; NOADX-NEXT: movzbl %dil, %ecx
+; NOADX-NEXT: movl $10, %eax
+; NOADX-NEXT: cmovnel %ecx, %eax
+; NOADX-NEXT: # kill: def $al killed $al killed $eax
+; NOADX-NEXT: retq
+ %ssub = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i8
+ %sum = add i8 %a, %b
+ %res = add i8 %sum, %ov.ext
+ %cmp = icmp eq i8 %res, 0
+ %sel = select i1 %cmp, i8 10, i8 %res
+ ret i8 %sel
+}
+
+define i16 @adox_test_flags_i16(i16 %a, i16 %b, i8 %c, i8 %d) {
+; NDD-LABEL: adox_test_flags_i16:
+; NDD: # %bb.0:
+; NDD-NEXT: addb %cl, %dl, %al
+; NDD-NEXT: adoxl %esi, %edi, %eax
+; NDD-NEXT: testw %ax, %ax
+; NDD-NEXT: movl $10, %ecx
+; NDD-NEXT: cmovel %ecx, %eax
+; NDD-NEXT: # kill: def $ax killed $ax killed $eax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_flags_i16:
+; ADX: # %bb.0:
+; ADX-NEXT: addb %cl, %dl
+; ADX-NEXT: adoxl %esi, %edi
+; ADX-NEXT: testw %di, %di
+; ADX-NEXT: movl $10, %eax
+; ADX-NEXT: cmovnel %edi, %eax
+; ADX-NEXT: # kill: def $ax killed $ax killed $eax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_flags_i16:
+; NOADX: # %bb.0:
+; NOADX-NEXT: # kill: def $esi killed $esi def $rsi
+; NOADX-NEXT: # kill: def $edi killed $edi def $rdi
+; NOADX-NEXT: xorl %r8d, %r8d
+; NOADX-NEXT: addb %cl, %dl
+; NOADX-NEXT: seto %r8b
+; NOADX-NEXT: addl %edi, %r8d
+; NOADX-NEXT: addl %esi, %r8d
+; NOADX-NEXT: testw %r8w, %r8w
+; NOADX-NEXT: movl $10, %eax
+; NOADX-NEXT: cmovnel %r8d, %eax
+; NOADX-NEXT: # kill: def $ax killed $ax killed $eax
+; NOADX-NEXT: retq
+ %ssub = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i16
+ %sum = add i16 %a, %b
+ %res = add i16 %sum, %ov.ext
+ %cmp = icmp eq i16 %res, 0
+ %sel = select i1 %cmp, i16 10, i16 %res
+ ret i16 %sel
+}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/X86/adox.ll b/llvm/test/CodeGen/X86/adox.ll
new file mode 100644
index 0000000000000..10f5216b4a45a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/adox.ll
@@ -0,0 +1,273 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+adx,+ndd | FileCheck %s --check-prefixes=CHECK,NDD
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+adx | FileCheck %s --check-prefixes=CHECK,ADX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-adx | FileCheck %s --check-prefixes=CHECK,NOADX
+
+define i32 @adox_test_i32(i32 %a, i32 %b, i8 %c, i8 %d) {
+; NDD-LABEL: adox_test_i32:
+; NDD: # %bb.0:
+; NDD-NEXT: cmpb %cl, %dl
+; NDD-NEXT: adoxl %esi, %edi, %eax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_i32:
+; ADX: # %bb.0:
+; ADX-NEXT: movl %edi, %eax
+; ADX-NEXT: cmpb %cl, %dl
+; ADX-NEXT: adoxl %esi, %eax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_i32:
+; NOADX: # %bb.0:
+; NOADX-NEXT: # kill: def $esi killed $esi def $rsi
+; NOADX-NEXT: # kill: def $edi killed $edi def $rdi
+; NOADX-NEXT: xorl %eax, %eax
+; NOADX-NEXT: cmpb %cl, %dl
+; NOADX-NEXT: seto %al
+; NOADX-NEXT: addl %edi, %eax
+; NOADX-NEXT: addl %esi, %eax
+; NOADX-NEXT: retq
+ %ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i32
+ %sum = add i32 %a, %b
+ %res = add i32 %sum, %ov.ext
+ ret i32 %res
+}
+
+define i64 @adox_test_i64(i64 %a, i64 %b, i8 %c, i8 %d) {
+; NDD-LABEL: adox_test_i64:
+; NDD: # %bb.0:
+; NDD-NEXT: cmpb %cl, %dl
+; NDD-NEXT: adoxq %rsi, %rdi, %rax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_i64:
+; ADX: # %bb.0:
+; ADX-NEXT: movq %rdi, %rax
+; ADX-NEXT: cmpb %cl, %dl
+; ADX-NEXT: adoxq %rsi, %rax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_i64:
+; NOADX: # %bb.0:
+; NOADX-NEXT: xorl %eax, %eax
+; NOADX-NEXT: cmpb %cl, %dl
+; NOADX-NEXT: seto %al
+; NOADX-NEXT: addq %rdi, %rax
+; NOADX-NEXT: addq %rsi, %rax
+; NOADX-NEXT: retq
+ %ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i64
+ %sum = add i64 %a, %b
+ %res = add i64 %sum, %ov.ext
+ ret i64 %res
+}
+
+declare { i8, i1 } @llvm.ssub.with.overflow.i8(i8, i8)
+
+define i32 @adox_test_i32_mem(i32 %a, ptr %b_ptr, i8 %c, i8 %d) {
+; NDD-LABEL: adox_test_i32_mem:
+; NDD: # %bb.0:
+; NDD-NEXT: cmpb %cl, %dl
+; NDD-NEXT: adoxl (%rsi), %edi, %eax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_i32_mem:
+; ADX: # %bb.0:
+; ADX-NEXT: movl %edi, %eax
+; ADX-NEXT: cmpb %cl, %dl
+; ADX-NEXT: adoxl (%rsi), %eax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_i32_mem:
+; NOADX: # %bb.0:
+; NOADX-NEXT: xorl %eax, %eax
+; NOADX-NEXT: cmpb %cl, %dl
+; NOADX-NEXT: seto %al
+; NOADX-NEXT: addl (%rsi), %edi
+; NOADX-NEXT: addl %edi, %eax
+; NOADX-NEXT: retq
+ %b = load i32, ptr %b_ptr
+ %ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i32
+ %add = add i32 %a, %b
+ %add2 = add i32 %add, %ov.ext
+ ret i32 %add2
+}
+
+define i64 @adox_test_i64_mem(i64 %a, ptr %b_ptr, i8 %c, i8 %d) {
+; NDD-LABEL: adox_test_i64_mem:
+; NDD: # %bb.0:
+; NDD-NEXT: cmpb %cl, %dl
+; NDD-NEXT: adoxq (%rsi), %rdi, %rax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_i64_mem:
+; ADX: # %bb.0:
+; ADX-NEXT: movq %rdi, %rax
+; ADX-NEXT: cmpb %cl, %dl
+; ADX-NEXT: adoxq (%rsi), %rax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_i64_mem:
+; NOADX: # %bb.0:
+; NOADX-NEXT: xorl %eax, %eax
+; NOADX-NEXT: cmpb %cl, %dl
+; NOADX-NEXT: seto %al
+; NOADX-NEXT: addq (%rsi), %rdi
+; NOADX-NEXT: addq %rdi, %rax
+; NOADX-NEXT: retq
+ %b = load i64, ptr %b_ptr
+ %ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i64
+ %add = add i64 %a, %b
+ %add2 = add i64 %add, %ov.ext
+ ret i64 %add2
+}
+
+define i32 @adox_test_sadd_i32(i32 %a, i32 %b, i8 %c, i8 %d) {
+; NDD-LABEL: adox_test_sadd_i32:
+; NDD: # %bb.0:
+; NDD-NEXT: addb %cl, %dl, %al
+; NDD-NEXT: adoxl %esi, %edi, %eax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_sadd_i32:
+; ADX: # %bb.0:
+; ADX-NEXT: movl %edi, %eax
+; ADX-NEXT: addb %cl, %dl
+; ADX-NEXT: adoxl %esi, %eax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_sadd_i32:
+; NOADX: # %bb.0:
+; NOADX-NEXT: # kill: def $esi killed $esi def $rsi
+; NOADX-NEXT: # kill: def $edi killed $edi def $rdi
+; NOADX-NEXT: xorl %eax, %eax
+; NOADX-NEXT: addb %cl, %dl
+; NOADX-NEXT: seto %al
+; NOADX-NEXT: addl %edi, %eax
+; NOADX-NEXT: addl %esi, %eax
+; NOADX-NEXT: retq
+ %sadd = call { i8, i1 } @llvm.sadd.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %sadd, 1
+ %ov.ext = zext i1 %ov to i32
+ %add = add i32 %a, %b
+ %add2 = add i32 %add, %ov.ext
+ ret i32 %add2
+}
+
+declare { i8, i1 } @llvm.sadd.with.overflow.i8(i8, i8)
+
+define i16 @adox_test_i16(i16 %a, i16 %b, i8 %c, i8 %d) {
+; NDD-LABEL: adox_test_i16:
+; NDD: # %bb.0:
+; NDD-NEXT: cmpb %cl, %dl
+; NDD-NEXT: adoxl %esi, %edi, %eax
+; NDD-NEXT: # kill: def $ax killed $ax killed $eax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_i16:
+; ADX: # %bb.0:
+; ADX-NEXT: movl %edi, %eax
+; ADX-NEXT: cmpb %cl, %dl
+; ADX-NEXT: adoxl %esi, %eax
+; ADX-NEXT: # kill: def $ax killed $ax killed $eax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_i16:
+; NOADX: # %bb.0:
+; NOADX-NEXT: # kill: def $esi killed $esi def $rsi
+; NOADX-NEXT: # kill: def $edi killed $edi def $rdi
+; NOADX-NEXT: xorl %eax, %eax
+; NOADX-NEXT: cmpb %cl, %dl
+; NOADX-NEXT: seto %al
+; NOADX-NEXT: addl %edi, %eax
+; NOADX-NEXT: addl %esi, %eax
+; NOADX-NEXT: # kill: def $ax killed $ax killed $eax
+; NOADX-NEXT: retq
+ %ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i16
+ %sum = add i16 %a, %b
+ %res = add i16 %sum, %ov.ext
+ ret i16 %res
+}
+
+define i8 @adox_test_i8(i8 %a, i8 %b, i8 %c, i8 %d) {
+; NDD-LABEL: adox_test_i8:
+; NDD: # %bb.0:
+; NDD-NEXT: cmpb %cl, %dl
+; NDD-NEXT: adoxl %esi, %edi, %eax
+; NDD-NEXT: # kill: def $al killed $al killed $eax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_i8:
+; ADX: # %bb.0:
+; ADX-NEXT: movl %edi, %eax
+; ADX-NEXT: cmpb %cl, %dl
+; ADX-NEXT: adoxl %esi, %eax
+; ADX-NEXT: # kill: def $al killed $al killed $eax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_i8:
+; NOADX: # %bb.0:
+; NOADX-NEXT: # kill: def $esi killed $esi def $rsi
+; NOADX-NEXT: # kill: def $edi killed $edi def $rdi
+; NOADX-NEXT: cmpb %cl, %dl
+; NOADX-NEXT: seto %cl
+; NOADX-NEXT: leal (%rdi,%rsi), %eax
+; NOADX-NEXT: addb %cl, %al
+; NOADX-NEXT: # kill: def $al killed $al killed $eax
+; NOADX-NEXT: retq
+ %ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i8
+ %sum = add i8 %a, %b
+ %res = add i8 %sum, %ov.ext
+ ret i8 %res
+}
+
+define i32 @adox_test_sub_i32(i32 %a, i32 %b, i8 %c, i8 %d) {
+; NDD-LABEL: adox_test_sub_i32:
+; NDD: # %bb.0:
+; NDD-NEXT: xorl %eax, %eax
+; NDD-NEXT: cmpb %cl, %dl
+; NDD-NEXT: seto %al
+; NDD-NEXT: subl %esi, %edi
+; NDD-NEXT: subl %eax, %edi, %eax
+; NDD-NEXT: retq
+;
+; ADX-LABEL: adox_test_sub_i32:
+; ADX: # %bb.0:
+; ADX-NEXT: movl %edi, %eax
+; ADX-NEXT: xorl %edi, %edi
+; ADX-NEXT: cmpb %cl, %dl
+; ADX-NEXT: seto %dil
+; ADX-NEXT: subl %esi, %eax
+; ADX-NEXT: subl %edi, %eax
+; ADX-NEXT: retq
+;
+; NOADX-LABEL: adox_test_sub_i32:
+; NOADX: # %bb.0:
+; NOADX-NEXT: movl %edi, %eax
+; NOADX-NEXT: xorl %edi, %edi
+; NOADX-NEXT: cmpb %cl, %dl
+; NOADX-NEXT: seto %dil
+; NOADX-NEXT: subl %esi, %eax
+; NOADX-NEXT: subl %edi, %eax
+; NOADX-NEXT: retq
+ %ssub = call { i8, i1 } @llvm.ssub.with.overflow.i8(i8 %c, i8 %d)
+ %ov = extractvalue { i8, i1 } %ssub, 1
+ %ov.ext = zext i1 %ov to i32
+ %sum = sub i32 %a, %b
+ %res = sub i32 %sum, %ov.ext
+ ret i32 %res
+}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
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