[llvm] [BOLT][RISCV] Support Zibi (PR #219285)

[Pengcheng Wang via llvm-commits]

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wangpc-pp wrote:

Not for this PR: this partially duplicates `llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp:getInvertedBranchOp` (these cases are different because we are using pseudos in MIR, but the functionality is the same)? I don't know if there is a way to get this information from target tooks.

https://github.com/llvm/llvm-project/pull/219285