[llvm] [WebAssembly] Add v8f16 bitselect pattern (PR #218954)

[Anutosh Bhat via llvm-commits]

https://github.com/anutosh491 updated https://github.com/llvm/llvm-project/pull/218954

>From f83dd0cf8608f55b64fb8d5f774786e2b3d23bef Mon Sep 17 00:00:00 2001
From: anutosh491 <andersonbhat491 at gmail.com>
Date: Wed, 26 Aug 2026 20:45:33 +0530
Subject: [PATCH] [WebAssembly] Add v8f16 bitselect pattern

---
 llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td |  2 +-
 llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll     | 12 ++++++++++++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
index 3e9783a9d1f25..f2800aebd78e3 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -903,7 +903,7 @@ defm BITSELECT :
   SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins), [],
          "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 82>;
 
-foreach vec = StdVecs in
+foreach vec = AllVecs in
 def : Pat<(vec.vt (int_wasm_bitselect
             (vec.vt V128:$v1), (vec.vt V128:$v2), (vec.vt V128:$c))),
           (BITSELECT $v1, $v2, $c)>;
diff --git a/llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll b/llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
index 26722f137fa06..4f0d3222858e1 100644
--- a/llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
+++ b/llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
@@ -89,6 +89,18 @@ define <8 x half> @insert_lane_v8f16(<8 x half> %v, half %x) {
   ret <8 x half> %r
 }
 
+; CHECK-LABEL: bitselect_v8f16:
+; CHECK:       v128.bitselect $push0=, $0, $1, $2
+; CHECK-NEXT:  return $pop0
+declare <8 x half> @llvm.wasm.bitselect.v8f16(<8 x half>, <8 x half>,
+                                              <8 x half>)
+define <8 x half> @bitselect_v8f16(<8 x half> %a, <8 x half> %b,
+                                    <8 x half> %mask) {
+  %result = call <8 x half> @llvm.wasm.bitselect.v8f16(
+      <8 x half> %a, <8 x half> %b, <8 x half> %mask)
+  ret <8 x half> %result
+}
+
 ; CHECK-LABEL: select_v8f16:
 ; CHECK:       v128.select $push0=, $1, $2, $0
 ; CHECK-NEXT:  return $pop0