[llvm] [AArch64][SVE] - Fix crash Possible incorrect use of EVT::getVectorNumElements(). (PR #218733)

[Pawan Nirpal via llvm-commits]

https://github.com/pawan-nirpal-031 updated https://github.com/llvm/llvm-project/pull/218733

>From 55ca693ffca3a72f5a02ebbb86f12afa94a0145e Mon Sep 17 00:00:00 2001
From: Pawan Nirpal <pnirpal at qti.qualcomm.com>
Date: Tue, 25 Aug 2026 10:27:37 -0700
Subject: [PATCH 1/2] [AArch64][SVE] - Fix crash  Possible incorrect use of
 EVT::getVectorNumElements()

---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp     |  4 ++--
 .../CodeGen/AArch64/sve-usubsat-dag-combine.ll    | 15 +++++++++++++++
 2 files changed, 17 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/AArch64/sve-usubsat-dag-combine.ll

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 28a8cb9409648..4a9b316105bfe 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4721,9 +4721,9 @@ SDValue DAGCombiner::visitSUBSAT(SDNode *N) {
       for (unsigned NarrowBits = PowerOf2Ceil(ActiveBits);
            NarrowBits != 0 && NarrowBits < ScalarBits; NarrowBits *= 2) {
         unsigned Scale = ScalarBits / NarrowBits;
-        unsigned NumElts = VT.getVectorNumElements() * Scale;
+        ElementCount ScaledEC = VT.getVectorElementCount() * Scale;
         MVT NarrowSVT = MVT::getIntegerVT(NarrowBits);
-        MVT NarrowVT = MVT::getVectorVT(NarrowSVT, NumElts);
+        EVT NarrowVT = EVT::getVectorVT(*DAG.getContext(), NarrowSVT, ScaledEC);
 
         if (!TLI.isOperationLegalOrCustom(ISD::USUBSAT, NarrowVT))
           continue;
diff --git a/llvm/test/CodeGen/AArch64/sve-usubsat-dag-combine.ll b/llvm/test/CodeGen/AArch64/sve-usubsat-dag-combine.ll
new file mode 100644
index 0000000000000..1d5c38ec6706a
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-usubsat-dag-combine.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+define <vscale x 8 x i32> @blend_heat_16bit(<vscale x 8 x i32> %0) #0 {
+; CHECK-LABEL: blend_heat_16bit:
+; CHECK:       // %bb.0: // %.lr.ph
+; CHECK-NEXT:    mov z2.s, #1 // =0x1
+; CHECK-NEXT:    uqsub z0.s, z2.s, z0.s
+; CHECK-NEXT:    uqsub z1.s, z2.s, z1.s
+; CHECK-NEXT:    ret
+.lr.ph:
+  %1 = call <vscale x 8 x i32> @llvm.usub.sat.nxv8i32(<vscale x 8 x i32> splat (i32 1), <vscale x 8 x i32> %0)
+  ret <vscale x 8 x i32> %1
+}
+

>From 7956d31e5e879e1c73fa030909e8d657d200ed70 Mon Sep 17 00:00:00 2001
From: Pawan Nirpal <pawannirpal at gmail.com>
Date: Thu, 27 Aug 2026 19:49:59 +0530
Subject: [PATCH 2/2] Apply suggestion from @paulwalker-arm

Co-authored-by: Paul Walker <paul.walker at arm.com>
---
 llvm/test/CodeGen/AArch64/sve-usubsat-dag-combine.ll | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/test/CodeGen/AArch64/sve-usubsat-dag-combine.ll b/llvm/test/CodeGen/AArch64/sve-usubsat-dag-combine.ll
index 1d5c38ec6706a..bb1c1611e157e 100644
--- a/llvm/test/CodeGen/AArch64/sve-usubsat-dag-combine.ll
+++ b/llvm/test/CodeGen/AArch64/sve-usubsat-dag-combine.ll
@@ -1,7 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
 
-define <vscale x 8 x i32> @blend_heat_16bit(<vscale x 8 x i32> %0) #0 {
+define <vscale x 8 x i32> @blend_heat_16bit(<vscale x 8 x i32> %0) {
 ; CHECK-LABEL: blend_heat_16bit:
 ; CHECK:       // %bb.0: // %.lr.ph
 ; CHECK-NEXT:    mov z2.s, #1 // =0x1