[llvm] [AMDGPU] Fold redundant inf/nan checks into frexp instructions (PR #214936)

[Yaxun Liu via llvm-commits]

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@@ -18935,6 +18935,114 @@ SDValue SITargetLowering::performClampCombine(SDNode *N,
   return getCanonicalConstantFP(DCI.DAG, SDLoc(N), N->getValueType(0), F);
 }
 
+SDValue
+SITargetLowering::performFrexpSelectCombine(SDNode *N,
+                                            DAGCombinerInfo &DCI) const {
+  // This optimization only applies when the hardware handles inf/nan correctly.
+  if (Subtarget->hasFractBug())
+    return SDValue();
+
+  SDValue Cond = N->getOperand(0);
+  SDValue TrueVal = N->getOperand(1);
+  SDValue FalseVal = N->getOperand(2);
+
+  // Identify which operand is the frexp result and which is the zero constant.
+  // Pattern 1: select cond, 0, frexp_result (cond true -> return 0)
+  // Pattern 2: select cond, frexp_result, 0 (cond false -> return 0)
+  SDValue FrexpVal;
+  SDValue ZeroVal;
+  bool CondSelectsZero; // If true, condition=true selects zero
+
+  // Check if FrexpVal comes from ISD::FFREXP or amdgcn_frexp_exp/mant
+  // intrinsics.
+  SDValue FrexpInput;
+  auto isFrexp = [&FrexpInput](SDValue V) {
+    if (V.getOpcode() == ISD::FFREXP) {
+      FrexpInput = V.getOperand(0);
+      return true;
+    }
+    if (sd_match(V, m_IntrinsicWOChain<Intrinsic::amdgcn_frexp_exp>(
+                        m_Value(FrexpInput))) ||
+        sd_match(V, m_IntrinsicWOChain<Intrinsic::amdgcn_frexp_mant>(
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yxsamliu wrote:

According to the [CDNA4 ISA manual](https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna4-instruction-set-architecture.pdf), `V_FREXP_MANT_F32` returns its input for Inf/NaN, not zero. Removing this select can therefore change `0.0` to NaN. Could you restrict this combine to `frexp_exp` and, if possible, run an E2E test on AMDGPU hardware to verify it?

https://github.com/llvm/llvm-project/pull/214936