[llvm] [AMDGPU] Handle register variant S_SETREG when fixing VGPR MSB clobbers (PR #218941)

[Arseniy Obolenskiy via llvm-commits]

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@@ -197,20 +197,24 @@ class AMDGPULowerVGPREncoding {
   MachineBasicBlock::instr_iterator
   handleCoissue(MachineBasicBlock::instr_iterator I);
 
-  /// S_SET_VGPR_MSB immediately after S_SETREG_IMM32_B32 targeting MODE is
+  /// S_SET_VGPR_MSB immediately after an S_SETREG variant targeting MODE is
   /// silently dropped on GFX1250. When set, the next S_SET_VGPR_MSB insertion
   /// must be preceded by S_NOP to avoid the hazard.
   bool needNopBeforeSetVGPRMSB(MachineBasicBlock::instr_iterator I);
 
-  /// Handle S_SETREG_IMM32_B32 targeting MODE register. On certain hardware,
+  /// Handle an S_SETREG variant targeting MODE register. On certain hardware,
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aobolensk wrote:

Thanks, fixed

https://github.com/llvm/llvm-project/pull/218941