[llvm] [AMDGPU] Only treat unconditional branches as implicit XCNT drains (PR #219206)
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Thu Aug 27 06:09:24 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Madhur Kumar (MadhurKumar004)
<details>
<summary>Changes</summary>
fixes: https://github.com/llvm/llvm-project/issues/213394
---
Full diff: https://github.com/llvm/llvm-project/pull/219206.diff
5 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+2-1)
- (modified) llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll (+2)
- (modified) llvm/test/CodeGen/AMDGPU/wait-xcnt-drain.mir (+2)
- (added) llvm/test/CodeGen/AMDGPU/wait-xcnt-execz-fallthrough.mir (+43)
- (modified) llvm/test/CodeGen/AMDGPU/wait-xcnt.mir (+1-2)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index bc419d813f171..ac30f5b9999d9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3594,7 +3594,8 @@ void SIInstrInfo::insertSelect(MachineBasicBlock &MBB,
bool SIInstrInfo::isXcntDrain(const MachineInstr &MI) {
- if (MI.isBranch() || MI.isCall() || MI.isReturn() || MI.isIndirectBranch())
+ if (MI.isUnconditionalBranch() || MI.isCall() || MI.isReturn() ||
+ MI.isIndirectBranch())
return true;
switch (MI.getOpcode()) {
diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
index 1c7da39fbccc6..65d1fe4ef965b 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
@@ -13053,6 +13053,7 @@ define void @flat_atomic_fmax_f64_saddr_nortn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: ; %bb.3: ; %atomicrmw.private
; GFX1250-SDAG-NEXT: s_sub_co_i32 s2, s0, src_flat_scratch_base_lo
; GFX1250-SDAG-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX1250-SDAG-NEXT: s_cselect_b32 s0, s2, -1
; GFX1250-SDAG-NEXT: scratch_load_b64 v[2:3], off, s0
@@ -13360,6 +13361,7 @@ define void @flat_atomic_fmin_f64_saddr_nortn(ptr inreg %ptr, double %data) {
; GFX1250-SDAG-NEXT: ; %bb.3: ; %atomicrmw.private
; GFX1250-SDAG-NEXT: s_sub_co_i32 s2, s0, src_flat_scratch_base_lo
; GFX1250-SDAG-NEXT: s_cmp_lg_u64 s[0:1], 0
+; GFX1250-SDAG-NEXT: s_wait_xcnt 0x0
; GFX1250-SDAG-NEXT: v_max_num_f64_e32 v[0:1], v[0:1], v[0:1]
; GFX1250-SDAG-NEXT: s_cselect_b32 s0, s2, -1
; GFX1250-SDAG-NEXT: scratch_load_b64 v[2:3], off, s0
diff --git a/llvm/test/CodeGen/AMDGPU/wait-xcnt-drain.mir b/llvm/test/CodeGen/AMDGPU/wait-xcnt-drain.mir
index a7b5247c40e09..ee9d7a461a8a2 100644
--- a/llvm/test/CodeGen/AMDGPU/wait-xcnt-drain.mir
+++ b/llvm/test/CodeGen/AMDGPU/wait-xcnt-drain.mir
@@ -22,12 +22,14 @@ body: |
; GCN-NEXT: bb.1:
; GCN-NEXT: liveins: $vgpr3
; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: S_WAIT_XCNT 0
; GCN-NEXT: $vgpr2 = V_LSHLREV_B32_e64 16, $vgpr3, implicit $exec
; GCN-NEXT: S_ENDPGM 0
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
; GCN-NEXT: liveins: $vgpr3
; GCN-NEXT: {{ $}}
+ ; GCN-NEXT: S_WAIT_XCNT 0
; GCN-NEXT: $vgpr2 = V_LSHLREV_B32_e64 32, $vgpr3, implicit $exec
; GCN-NEXT: S_ENDPGM 0
bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/wait-xcnt-execz-fallthrough.mir b/llvm/test/CodeGen/AMDGPU/wait-xcnt-execz-fallthrough.mir
new file mode 100644
index 0000000000000..b4ea992fb1400
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/wait-xcnt-execz-fallthrough.mir
@@ -0,0 +1,43 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgpu12.50-amd-amdhsa -mcpu=gfx1250 \
+# RUN: -run-pass si-insert-waitcnts,si-pre-emit-peephole -o - %s | FileCheck %s
+
+---
+name: xcnt_execz_fallthrough
+tracksRegLiveness: true
+machineFunctionInfo:
+ isEntryFunction: true
+body: |
+ ; CHECK-LABEL: name: xcnt_execz_fallthrough
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+ ; CHECK-NEXT: liveins: $vgpr2, $vgpr3, $vgpr18, $vgpr19, $vgpr20, $vgpr21
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: S_SETREG_IMM32_B32 1, 1601, implicit-def $mode, implicit $mode
+ ; CHECK-NEXT: $sgpr64_sgpr65 = S_MOV_B64 0
+ ; CHECK-NEXT: V_NOP_e32 implicit $exec
+ ; CHECK-NEXT: GLOBAL_PREFETCH_B8_SADDR $sgpr64_sgpr65, undef $vgpr0, 0, 8, implicit $exec
+ ; CHECK-NEXT: GLOBAL_STORE_DWORDX4 killed $vgpr2_vgpr3, killed $vgpr18_vgpr19_vgpr20_vgpr21, 0, 0, implicit $exec
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.2(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: S_WAIT_XCNT 0
+ ; CHECK-NEXT: $vgpr2 = V_MOV_B32_e32 0, implicit $exec
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2:
+ ; CHECK-NEXT: S_ENDPGM 0
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $vgpr2, $vgpr3, $vgpr18, $vgpr19, $vgpr20, $vgpr21
+ GLOBAL_STORE_DWORDX4 killed $vgpr2_vgpr3, killed $vgpr18_vgpr19_vgpr20_vgpr21, 0, 0, implicit $exec
+ S_CBRANCH_EXECZ %bb.2, implicit $exec
+
+ bb.1:
+ successors: %bb.2
+ $vgpr2 = V_MOV_B32_e32 0, implicit $exec
+
+ bb.2:
+ S_ENDPGM 0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/wait-xcnt.mir b/llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
index 4bd0bf7180b91..c6fe985f5ea2c 100644
--- a/llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
+++ b/llvm/test/CodeGen/AMDGPU/wait-xcnt.mir
@@ -1317,9 +1317,8 @@ body: |
; GCN-NEXT: bb.2:
; GCN-NEXT: liveins: $sgpr0_sgpr1, $sgpr2, $vgpr2
; GCN-NEXT: {{ $}}
- ; GCN-NEXT: S_WAIT_XCNT 1
- ; GCN-NEXT: $vgpr1 = V_MOV_B32_e32 0, implicit $exec
; GCN-NEXT: S_WAIT_XCNT 0
+ ; GCN-NEXT: $vgpr1 = V_MOV_B32_e32 0, implicit $exec
; GCN-NEXT: $vgpr2 = V_MOV_B32_e32 0, implicit $exec
; GCN-NEXT: $sgpr0 = S_MOV_B32 $sgpr0
bb.0:
``````````
</details>
https://github.com/llvm/llvm-project/pull/219206
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