[llvm] [AArch64] Add DAG combine to widen v3i8/v4i8 VECTOR_MATCH needles (PR #218972)

[Benjamin Maxwell via llvm-commits]

================
@@ -1656,6 +1656,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
 
       for (MVT VT : {MVT::v16i1, MVT::v8i1, MVT::v16i8, MVT::v8i8})
         setOperationAction(ISD::VECTOR_MATCH, VT, Custom);
+
+      setTargetDAGCombine(ISD::VECTOR_MATCH);
----------------
MacDue wrote:

> It would have been nice if you tried the suggestion before dismissing it but for the avoidance of doubt the following matches this PR's output:

Sorry, I was not dismissing the suggestion. I was just trying to clarify things as I thought the operation legalization actions applied based on the switch in `VectorLegalizer::LegalizeOp`:

```c++
  case ISD::VECTOR_MATCH:
    Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
    break;
```

https://github.com/llvm/llvm-project/pull/218972