[llvm] [AArch64][SDAG] Enable +sme2p2/+sve2p2 lowering for compressstore (PR #218624)

[Benjamin Maxwell via llvm-commits]

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@@ -334,13 +334,21 @@ class AArch64TTIImpl final : public BasicTTIImplBase<AArch64TTIImpl> {
   }
 
   bool isElementTypeLegalForCompressStore(Type *Ty) const {
-    return Ty->isFloatTy() || Ty->isDoubleTy() || Ty->isIntegerTy(32) ||
-           Ty->isIntegerTy(64);
+    // 32-bit and 64-bit element types are legal if we have SVE.
+    if (Ty->getScalarSizeInBits() == 32 || Ty->getScalarSizeInBits() == 64)
+      return true;
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MacDue wrote:

It might be worth teaching the cost model about the cases that can be promoted to the SVE1 operations (e.g. (nx)v4i16 can be promoted to (nx)v4i32, so is legal without +sve2p2). 

No change required for this PR (other than maybe a TODO). 

https://github.com/llvm/llvm-project/pull/218624