[llvm] [NVPTX] Fix lowering of fabs and fneg (PR #219089)

[Lewis Crawford via llvm-commits]

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@@ -2244,6 +2248,73 @@ SDValue NVPTXTargetLowering::LowerFCOPYSIGN(SDValue Op,
   return DAG.getNode(NVPTXISD::FCOPYSIGN, DL, VT, In1, In2);
 }
 
+static bool isCanonicalizingFPOp(unsigned Opc) {
+  switch (Opc) {
+  case ISD::FADD:
+  case ISD::FSUB:
+  case ISD::FMUL:
+  case ISD::FDIV:
+  case ISD::FREM:
+  case ISD::FMA:
+  case ISD::FSQRT:
+  case ISD::FMINNUM:
+  case ISD::FMAXNUM:
+  case ISD::FMINIMUM:
+  case ISD::FMAXIMUM:
+  case ISD::FMINIMUMNUM:
+  case ISD::FMAXIMUMNUM:
+  case ISD::FCEIL:
+  case ISD::FFLOOR:
+  case ISD::FTRUNC:
+  case ISD::FRINT:
+  case ISD::FNEARBYINT:
+  case ISD::FROUNDEVEN:
+  case ISD::FROUND:
+  case ISD::FP_TO_SINT:
+  case ISD::FP_TO_UINT:
+  case ISD::FP_TO_SINT_SAT:
+  case ISD::FP_TO_UINT_SAT:
+  case ISD::FSIN:
+  case ISD::FCOS:
+  case ISD::FTANH:
+  // SETCC is not strictly canonicalizing, just eats the nan
+  case ISD::SETCC:
+    return true;
+  default:
+    return false;
+  }
+}
+
+static bool canUseNativeSignOp(SDValue Op, SelectionDAG &DAG) {
+  // A canonicalizing input is not enough: abs/neg still return an unspecified
+  // NaN for it. Only a non-NaN input makes the native op exact.
+  if (DAG.isKnownNeverNaN(Op.getOperand(0)))
+    return true;
+  return llvm::all_of(Op->users(), [](const SDNode *U) {
+    return isCanonicalizingFPOp(U->getOpcode());
+  });
+}
+
+static SDValue lowerFABSOrFNEG(SDValue Op, SelectionDAG &DAG) {
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LewisCrawford wrote:

This function could maybe do with a short summary comment explaining the 2 forms either instruction can take and why.

https://github.com/llvm/llvm-project/pull/219089