[llvm] [AArch64] Add DAG combine to widen v3i8/v4i8 VECTOR_MATCH needles (PR #218972)

[Paul Walker via llvm-commits]

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@@ -1656,6 +1656,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
 
       for (MVT VT : {MVT::v16i1, MVT::v8i1, MVT::v16i8, MVT::v8i8})
         setOperationAction(ISD::VECTOR_MATCH, VT, Custom);
+
+      setTargetDAGCombine(ISD::VECTOR_MATCH);
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paulwalker-arm wrote:

Using DAGCombiner for type legalisation should be the last resort and usually includes operation legalisation to emit something target specific. In this case you should be able to extend the above loop to include `MVT::v3i8, MVT::v4i8` and then add the necessary code or call to `LowerVectorMatch`.

https://github.com/llvm/llvm-project/pull/218972