[llvm] [AArch64] Fold four and eight way partial reductions with [SU]ADDLP (PR #214636)

[Paul Walker via llvm-commits]

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@@ -35082,6 +35090,13 @@ AArch64TargetLowering::LowerPARTIAL_REDUCE_MLA(SDValue Op,
     return DAG.getNode(ISD::SUB, DL, ResultVT, BiasedDot, BiasCorrection);
   }
 
+  // The wider Neon shapes left here have no single instruction, so leave them
+  // to the generic expansion, which chains the two-way reductions above.
+  if (!Subtarget->isSVEorStreamingSVEAvailable() &&
+      OpVT.isFixedLengthVector() &&
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paulwalker-arm wrote:

The isFixedLengthVector check is likely unnecessary because if SVE is not available and we get this far with a scalable vector then we've got bigger problems.

https://github.com/llvm/llvm-project/pull/214636