[llvm] [AMDGPU] Handle register variant S_SETREG when fixing VGPR MSB clobbers (PR #218941)

[Jay Foad via llvm-commits]

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@@ -197,20 +197,24 @@ class AMDGPULowerVGPREncoding {
   MachineBasicBlock::instr_iterator
   handleCoissue(MachineBasicBlock::instr_iterator I);
 
-  /// S_SET_VGPR_MSB immediately after S_SETREG_IMM32_B32 targeting MODE is
+  /// S_SET_VGPR_MSB immediately after an S_SETREG variant targeting MODE is
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jayfoad wrote:

Yes, this part applies to S_SETREG_B32 and S_SETREG_IMM32_B32.

https://github.com/llvm/llvm-project/pull/218941