[llvm] [AArch64][SDAG] Enable +sme2p2/+sve2p2 lowering for compressstore (PR #218624)

[Benjamin Maxwell via llvm-commits]

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@@ -334,13 +334,20 @@ class AArch64TTIImpl final : public BasicTTIImplBase<AArch64TTIImpl> {
   }
 
   bool isElementTypeLegalForCompressStore(Type *Ty) const {
-    return Ty->isFloatTy() || Ty->isDoubleTy() || Ty->isIntegerTy(32) ||
+    // For streaming SME2p2, only consider 8bit or 16bit Scalar types.
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MacDue wrote:

This is not correct with +SME2p2 you get all compact instructions.

https://github.com/llvm/llvm-project/pull/218624