[llvm] [RISCV] Disable generic DAG combines at -O0 to preserve debuggability (PR #219082)

[Jim Lin via llvm-commits]

tclin914 wrote:

> Doesn't this mean invalid immediate shift amounts won't get canonicalized. Or ANDing with all ones won't be removed. I think there might be some code in RISCVISelDAGToDAG.cpp for selecting shift+and that assume these things happened.

All three canonicalizations happen in `SelectionDAG::getNode`, not in DAGCombiner, so `disableGenericCombines()` doesn't turn them off.

Shift amount 0 and out-of-range shift amounts — `getNode` routes `SHL`/`SRA`/`SRL` through `SelectionDAG::simplifyShift` (`SelectionDAG.cpp:8588`), which does:

```cpp
  // shift 0, Y --> 0
  // shift X, 0 --> X
  if (isNullOrNullSplat(X) || isNullOrNullSplat(Y))
    return X;

  // shift X, C >= bitwidth(X) --> undef
  auto isShiftTooBig = [X](ConstantSDNode *Val) {
    return !Val || Val->getAPIntValue().uge(X.getScalarValueSizeInBits());
  };
  if (ISD::matchUnaryPredicate(Y, isShiftTooBig, true))
    return getUNDEF(X.getValueType());
```

AND with all ones — also `getNode`, at `SelectionDAG.cpp:8450`:

```cpp
    if (N2CV && N2CV->isAllOnes()) // X & -1 -> X
      return N1;
```
Since every node is constructed through `getNode` regardless of opt level, and legalization builds its nodes the same way, these invariants hold at `-O0` too. So the two asserts you're thinking of — `assert((C2 > 0 && C2 < XLen) && "Unexpected shift amount!")` in the `ISD::AND` case of `Select()` (`RISCVISelDAGToDAG.cpp:1520`, and again at `:1756` for the `SRA` sub-case) — are still satisfied.



https://github.com/llvm/llvm-project/pull/219082