[llvm] [AArch64] Fold four and eight way partial reductions with [SU]ADDLP (PR #214636)

[Adam Scott via llvm-commits]

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@@ -13984,6 +13984,46 @@ SDValue TargetLowering::expandPartialReduceMLA(SDNode *N,
     break;
   }
 
+  // A wide partial reduction is built from a ladder of narrower ones, a rung
+  // at a time, each halving the element count and doubling the width.
+  unsigned Opc = N->getOpcode();
+  if (Opc != ISD::PARTIAL_REDUCE_FMLA &&
+      MulOpVT.getVectorMinNumElements() > 2 * AccVT.getVectorMinNumElements() &&
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as4230 wrote:

Allowing the mixed case wasn't deliberate. I will switch to hasKnownScalarFactor..

https://github.com/llvm/llvm-project/pull/214636