[llvm] [AMDGPU] Handle register variant S_SETREG when fixing VGPR MSB clobbers (PR #218941)

[Arseniy Obolenskiy via llvm-commits]

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@@ -1252,6 +1252,19 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
     }
   }
 
+  /// \returns true if \p Opcode is any S_SETREG_B32/S_SETREG_IMM32_B32 variant.
+  static bool isSSetReg(unsigned Opcode) {
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aobolensk wrote:

Done

https://github.com/llvm/llvm-project/pull/218941