[llvm] 97c6103 - [AMDGPU] Downgrade cluster loads in strict mode (#218999)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 26 17:00:14 PDT 2026
Author: Stanislav Mekhanoshin
Date: 2026-08-26T17:00:09-07:00
New Revision: 97c6103e88df58931f5c1c1441355ff9aff0bbf6
URL: https://github.com/llvm/llvm-project/commit/97c6103e88df58931f5c1c1441355ff9aff0bbf6
DIFF: https://github.com/llvm/llvm-project/commit/97c6103e88df58931f5c1c1441355ff9aff0bbf6.diff
LOG: [AMDGPU] Downgrade cluster loads in strict mode (#218999)
Added:
Modified:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 96e0def779423..d9810e3d9fbd9 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -11792,12 +11792,31 @@ SITargetLowering::lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
M->getMemOperand());
}
+static void initializeM0ToZeroForClusterLoad(SDValue Op, SelectionDAG &DAG,
+ SDLoc DL) {
+ SDNode *N = Op.getNode();
+ SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
+ unsigned NumOperands = N->getNumOperands();
+ if (N->getOperand(NumOperands - 1) == Zero)
+ return;
+ SmallVector<SDValue, 7> Ops(N->ops());
+ Ops[NumOperands - 1] = Zero; // M0 = 0
+ DAG.UpdateNodeOperands(N, Ops);
+}
+
SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
SelectionDAG &DAG) const {
unsigned IntrID = Op.getConstantOperandVal(1);
SDLoc DL(Op);
switch (IntrID) {
+ case Intrinsic::amdgcn_cluster_load_b32:
+ case Intrinsic::amdgcn_cluster_load_b64:
+ case Intrinsic::amdgcn_cluster_load_b128: {
+ if (Subtarget->hasGFX1250_STRICT())
+ initializeM0ToZeroForClusterLoad(Op, DAG, DL);
+ return SDValue();
+ }
case Intrinsic::amdgcn_ds_ordered_add:
case Intrinsic::amdgcn_ds_ordered_swap: {
MemSDNode *M = cast<MemSDNode>(Op);
@@ -12587,6 +12606,14 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
unsigned IntrinsicID = Op.getConstantOperandVal(1);
switch (IntrinsicID) {
+ case Intrinsic::amdgcn_cluster_load_async_to_lds_b8:
+ case Intrinsic::amdgcn_cluster_load_async_to_lds_b32:
+ case Intrinsic::amdgcn_cluster_load_async_to_lds_b64:
+ case Intrinsic::amdgcn_cluster_load_async_to_lds_b128: {
+ if (Subtarget->hasGFX1250_STRICT())
+ initializeM0ToZeroForClusterLoad(Op, DAG, DL);
+ return SDValue();
+ }
case Intrinsic::amdgcn_exp_compr: {
SDValue Src0 = Op.getOperand(4);
SDValue Src1 = Op.getOperand(5);
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
index 097d00879387f..a54ab6563a61b 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.async.to.lds.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu12.50s < %s | FileCheck -check-prefixes=GFX1250,GFX1250S-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.50s < %s | FileCheck -check-prefixes=GFX1250,GFX1250S-GISEL %s
declare void @llvm.amdgcn.cluster.load.async.to.lds.b8(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %offset, i32 %cpol, i32 %mask)
declare void @llvm.amdgcn.cluster.load.async.to.lds.b32(ptr addrspace(1) %gaddr, ptr addrspace(3) %laddr, i32 %offset, i32 %cpol, i32 %mask)
@@ -33,6 +35,31 @@ define amdgpu_ps void @cluster_load_async_to_lds_b8_vaddr(ptr addrspace(1) %gadd
; GFX1250-GISEL-NEXT: s_mov_b32 m0, s0
; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b8 v2, v[0:1], off offset:16 th:TH_LOAD_NT
; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b8_vaddr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b8 v2, v[0:1], off offset:16 th:TH_LOAD_NT
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b8_vaddr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX1250S-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
+; GFX1250S-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250S-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s0
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b8 v2, v[0:1], off offset:16 th:TH_LOAD_NT
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4
call void @llvm.amdgcn.cluster.load.async.to.lds.b8(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 1, i32 %mask)
@@ -63,6 +90,30 @@ define amdgpu_ps void @cluster_load_async_to_lds_b8_vaddr_imm_mask(ptr addrspace
; GFX1250-GISEL-NEXT: s_mov_b32 m0, 15
; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b8 v2, v[0:1], off offset:16
; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b8_vaddr_imm_mask:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b8 v2, v[0:1], off offset:16
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b8_vaddr_imm_mask:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
+; GFX1250S-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250S-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, 15
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b8 v2, v[0:1], off offset:16
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4
call void @llvm.amdgcn.cluster.load.async.to.lds.b8(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 15)
@@ -70,16 +121,49 @@ entry:
}
define amdgpu_ps void @cluster_load_async_to_lds_b8_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask) {
-; GFX1250-LABEL: cluster_load_async_to_lds_b8_saddr:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_mov_b32_e32 v1, 32
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: cluster_load_async_to_lds_b8 v0, v1, s[0:1] offset:16
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b8_saddr:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b8 v0, v1, s[0:1] offset:16
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b8_saddr:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b8 v0, v1, s[0:1] offset:16
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b8_saddr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b8 v0, v1, s[0:1] offset:16
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b8_saddr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b8 v0, v1, s[0:1] offset:16
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4
call void @llvm.amdgcn.cluster.load.async.to.lds.b8(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 %mask)
@@ -112,6 +196,31 @@ define amdgpu_ps void @cluster_load_async_to_lds_b32_vaddr(ptr addrspace(1) %gad
; GFX1250-GISEL-NEXT: s_mov_b32 m0, s0
; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b32 v2, v[0:1], off offset:16 th:TH_LOAD_HT scope:SCOPE_SE
; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b32_vaddr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b32 v2, v[0:1], off offset:16 th:TH_LOAD_HT scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b32_vaddr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX1250S-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
+; GFX1250S-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250S-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s0
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b32 v2, v[0:1], off offset:16 th:TH_LOAD_HT scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4
call void @llvm.amdgcn.cluster.load.async.to.lds.b32(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 10, i32 %mask)
@@ -142,6 +251,30 @@ define amdgpu_ps void @cluster_load_async_to_lds_b32_vaddr_imm_mask(ptr addrspac
; GFX1250-GISEL-NEXT: s_mov_b32 m0, 15
; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b32 v2, v[0:1], off offset:16
; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b32_vaddr_imm_mask:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b32 v2, v[0:1], off offset:16
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b32_vaddr_imm_mask:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
+; GFX1250S-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250S-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, 15
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b32 v2, v[0:1], off offset:16
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4
call void @llvm.amdgcn.cluster.load.async.to.lds.b32(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 15)
@@ -149,16 +282,49 @@ entry:
}
define amdgpu_ps void @cluster_load_async_to_lds_b32_saddr( ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask) {
-; GFX1250-LABEL: cluster_load_async_to_lds_b32_saddr:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_mov_b32_e32 v1, 32
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b32_saddr:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b32_saddr:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b32_saddr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b32_saddr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4
call void @llvm.amdgcn.cluster.load.async.to.lds.b32(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 %mask)
@@ -191,6 +357,31 @@ define amdgpu_ps void @cluster_load_async_to_lds_b64_vaddr(ptr addrspace(1) %gad
; GFX1250-GISEL-NEXT: s_mov_b32 m0, s0
; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b64 v2, v[0:1], off offset:16 th:TH_LOAD_NT_HT scope:SCOPE_DEV
; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b64_vaddr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b64 v2, v[0:1], off offset:16 th:TH_LOAD_NT_HT scope:SCOPE_DEV
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b64_vaddr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX1250S-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
+; GFX1250S-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250S-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s0
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b64 v2, v[0:1], off offset:16 th:TH_LOAD_NT_HT scope:SCOPE_DEV
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4
call void @llvm.amdgcn.cluster.load.async.to.lds.b64(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 22, i32 %mask)
@@ -221,6 +412,30 @@ define amdgpu_ps void @cluster_load_async_to_lds_b64_vaddr_imm_mask( ptr addrspa
; GFX1250-GISEL-NEXT: s_movk_i32 m0, 0x7f
; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b64 v2, v[0:1], off offset:16
; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b64_vaddr_imm_mask:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b64 v2, v[0:1], off offset:16
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b64_vaddr_imm_mask:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
+; GFX1250S-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250S-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1250S-GISEL-NEXT: s_movk_i32 m0, 0x7f
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b64 v2, v[0:1], off offset:16
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4
call void @llvm.amdgcn.cluster.load.async.to.lds.b64(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 127)
@@ -228,16 +443,49 @@ entry:
}
define amdgpu_ps void @cluster_load_async_to_lds_b64_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask) {
-; GFX1250-LABEL: cluster_load_async_to_lds_b64_saddr:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_mov_b32_e32 v1, 32
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: cluster_load_async_to_lds_b64 v0, v1, s[0:1] offset:16
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b64_saddr:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b64 v0, v1, s[0:1] offset:16
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b64_saddr:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b64 v0, v1, s[0:1] offset:16
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b64_saddr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b64 v0, v1, s[0:1] offset:16
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b64_saddr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b64 v0, v1, s[0:1] offset:16
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4
call void @llvm.amdgcn.cluster.load.async.to.lds.b64(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 %mask)
@@ -270,6 +518,31 @@ define amdgpu_ps void @cluster_load_async_to_lds_b128_vaddr(ptr addrspace(1) %ga
; GFX1250-GISEL-NEXT: s_mov_b32 m0, s0
; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b128 v2, v[0:1], off offset:16 th:TH_LOAD_BYPASS scope:SCOPE_SYS
; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b128_vaddr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b128 v2, v[0:1], off offset:16 th:TH_LOAD_BYPASS scope:SCOPE_SYS
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b128_vaddr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_readfirstlane_b32 s0, v3
+; GFX1250S-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
+; GFX1250S-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250S-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s0
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b128 v2, v[0:1], off offset:16 th:TH_LOAD_BYPASS scope:SCOPE_SYS
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4
call void @llvm.amdgcn.cluster.load.async.to.lds.b128(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 27, i32 %mask)
@@ -300,6 +573,30 @@ define amdgpu_ps void @cluster_load_async_to_lds_b128_vaddr_imm_mask(ptr addrspa
; GFX1250-GISEL-NEXT: s_movk_i32 m0, 0x7f
; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b128 v2, v[0:1], off offset:16
; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b128_vaddr_imm_mask:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 32, v[0:1]
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b128 v2, v[0:1], off offset:16
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b128_vaddr_imm_mask:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32
+; GFX1250S-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250S-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo
+; GFX1250S-GISEL-NEXT: s_movk_i32 m0, 0x7f
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b128 v2, v[0:1], off offset:16
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4
call void @llvm.amdgcn.cluster.load.async.to.lds.b128(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 127)
@@ -307,16 +604,49 @@ entry:
}
define amdgpu_ps void @cluster_load_async_to_lds_b128_saddr(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask) {
-; GFX1250-LABEL: cluster_load_async_to_lds_b128_saddr:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_mov_b32_e32 v1, 32
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: cluster_load_async_to_lds_b128 v0, v1, s[0:1] offset:16
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b128_saddr:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b128 v0, v1, s[0:1] offset:16
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b128_saddr:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b128 v0, v1, s[0:1] offset:16
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b128_saddr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b128 v0, v1, s[0:1] offset:16
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b128_saddr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_mov_b32_e32 v1, 32
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b128 v0, v1, s[0:1] offset:16
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4
call void @llvm.amdgcn.cluster.load.async.to.lds.b128(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 %mask)
@@ -324,15 +654,45 @@ entry:
}
define amdgpu_ps void @cluster_load_async_to_lds_b32_saddr_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask, i32 %idx) {
-; GFX1250-LABEL: cluster_load_async_to_lds_b32_saddr_scale_offset:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b32_saddr_scale_offset:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b32_saddr_scale_offset:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b32_saddr_scale_offset:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b32_saddr_scale_offset:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%idxprom = sext i32 %idx to i64
%gep = getelementptr i32, ptr addrspace(1) %gaddr, i64 %idxprom
@@ -341,15 +701,45 @@ entry:
}
define amdgpu_ps void @cluster_load_async_to_lds_b64_saddr_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask, i32 %idx) {
-; GFX1250-LABEL: cluster_load_async_to_lds_b64_saddr_scale_offset:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: cluster_load_async_to_lds_b64 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b64_saddr_scale_offset:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b64 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b64_saddr_scale_offset:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b64 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b64_saddr_scale_offset:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b64 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b64_saddr_scale_offset:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b64 v0, v1, s[0:1] offset:16 scale_offset th:TH_LOAD_NT
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%idxprom = sext i32 %idx to i64
%gep = getelementptr i64, ptr addrspace(1) %gaddr, i64 %idxprom
@@ -358,19 +748,61 @@ entry:
}
define amdgpu_ps void @cluster_load_async_to_lds_b64_saddr_no_scale_offset(ptr addrspace(1) inreg %gaddr, ptr addrspace(3) %laddr, i32 inreg %mask, i32 %idx) {
-; GFX1250-LABEL: cluster_load_async_to_lds_b64_saddr_no_scale_offset:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_mov_b32_e32 v2, v1
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-NEXT: v_ashrrev_i32_e32 v3, 31, v2
-; GFX1250-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 2, s[0:1]
-; GFX1250-NEXT: cluster_load_async_to_lds_b64 v0, v[2:3], off offset:16 th:TH_LOAD_NT
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_async_to_lds_b64_saddr_no_scale_offset:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, v1
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX1250-SDAG-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 2, s[0:1]
+; GFX1250-SDAG-NEXT: cluster_load_async_to_lds_b64 v0, v[2:3], off offset:16 th:TH_LOAD_NT
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_async_to_lds_b64_saddr_no_scale_offset:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, v1
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX1250-GISEL-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 2, s[0:1]
+; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b64 v0, v[2:3], off offset:16 th:TH_LOAD_NT
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b64_saddr_no_scale_offset:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_mov_b32_e32 v2, v1
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250S-SDAG-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX1250S-SDAG-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 2, s[0:1]
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b64 v0, v[2:3], off offset:16 th:TH_LOAD_NT
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b64_saddr_no_scale_offset:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_mov_b32_e32 v2, v1
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250S-GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX1250S-GISEL-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 2, s[0:1]
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b64 v0, v[2:3], off offset:16 th:TH_LOAD_NT
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%idxprom = sext i32 %idx to i64
%gep = getelementptr i32, ptr addrspace(1) %gaddr, i64 %idxprom
@@ -400,8 +832,32 @@ define amdgpu_ps void @cluster_load_async_to_lds_b32_saddr_sladdr(ptr addrspace(
; GFX1250-GISEL-NEXT: s_mov_b32 m0, s3
; GFX1250-GISEL-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16
; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_async_to_lds_b32_saddr_sladdr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_dual_mov_b32 v0, 32 :: v_dual_mov_b32 v1, s2
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_async_to_lds_b32 v1, v0, s[0:1] offset:16
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_async_to_lds_b32_saddr_sladdr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 32
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s3
+; GFX1250S-GISEL-NEXT: cluster_load_async_to_lds_b32 v0, v1, s[0:1] offset:16
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %gaddr, i32 4
call void @llvm.amdgcn.cluster.load.async.to.lds.b32(ptr addrspace(1) %gep, ptr addrspace(3) %laddr, i32 16, i32 0, i32 %mask)
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1250: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
index 698d59502ad3d..c12c10421e495 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cluster.load.ll
@@ -1,24 +1,64 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgpu12.50 -O3 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgpu12.50 -O3 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu12.50s -O3 < %s | FileCheck -check-prefixes=GFX1250,GFX1250S-SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu12.50s -O3 < %s | FileCheck -check-prefixes=GFX1250,GFX1250S-GISEL %s
declare i32 @llvm.amdgcn.cluster.load.b32.i32.p1(ptr addrspace(1), i32 %cpol, i32 %mask)
declare <2 x i32> @llvm.amdgcn.cluster.load.b64.v2i32.p1(ptr addrspace(1), i32 %cpol, i32 %mask)
declare <4 x i32> @llvm.amdgcn.cluster.load.b128.v4i32.p1(ptr addrspace(1), i32 %cpol, i32 %mask)
define amdgpu_ps void @cluster_load_b32_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use, i32 %mask) {
-; GFX1250-LABEL: cluster_load_b32_vaddr:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_readfirstlane_b32 s0, v4
-; GFX1250-NEXT: s_mov_b32 m0, s0
-; GFX1250-NEXT: cluster_load_b32 v0, v[0:1], off offset:32 th:TH_LOAD_NT
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b32 v[2:3], v0, off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_b32_vaddr:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s0
+; GFX1250-SDAG-NEXT: cluster_load_b32 v0, v[0:1], off offset:32 th:TH_LOAD_NT
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: global_store_b32 v[2:3], v0, off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_b32_vaddr:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s0
+; GFX1250-GISEL-NEXT: cluster_load_b32 v0, v[0:1], off offset:32 th:TH_LOAD_NT
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: global_store_b32 v[2:3], v0, off
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_b32_vaddr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_b32 v0, v[0:1], off offset:32 th:TH_LOAD_NT
+; GFX1250S-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-SDAG-NEXT: global_store_b32 v[2:3], v0, off
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_b32_vaddr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s0
+; GFX1250S-GISEL-NEXT: cluster_load_b32 v0, v[0:1], off offset:32 th:TH_LOAD_NT
+; GFX1250S-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-GISEL-NEXT: global_store_b32 v[2:3], v0, off
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
%val = call i32 @llvm.amdgcn.cluster.load.b32.i32.p1(ptr addrspace(1) %gep, i32 1, i32 %mask)
@@ -27,17 +67,53 @@ entry:
}
define amdgpu_ps void @cluster_load_b32_vaddr_imm_mask(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
-; GFX1250-LABEL: cluster_load_b32_vaddr_imm_mask:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: s_mov_b32 m0, 7
-; GFX1250-NEXT: cluster_load_b32 v0, v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b32 v[2:3], v0, off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_b32_vaddr_imm_mask:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, 7
+; GFX1250-SDAG-NEXT: cluster_load_b32 v0, v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: global_store_b32 v[2:3], v0, off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_b32_vaddr_imm_mask:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, 7
+; GFX1250-GISEL-NEXT: cluster_load_b32 v0, v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: global_store_b32 v[2:3], v0, off
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_b32_vaddr_imm_mask:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_b32 v0, v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-SDAG-NEXT: global_store_b32 v[2:3], v0, off
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_b32_vaddr_imm_mask:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, 7
+; GFX1250S-GISEL-NEXT: cluster_load_b32 v0, v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-GISEL-NEXT: global_store_b32 v[2:3], v0, off
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
%val = call i32 @llvm.amdgcn.cluster.load.b32.i32.p1(ptr addrspace(1) %gep, i32 10, i32 7)
@@ -46,18 +122,57 @@ entry:
}
define amdgpu_ps void @cluster_load_b32_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask) {
-; GFX1250-LABEL: cluster_load_b32_saddr:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_mov_b32_e32 v2, 0
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: cluster_load_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_b32_saddr:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: cluster_load_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_b32_saddr:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: cluster_load_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_b32_saddr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV
+; GFX1250S-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-SDAG-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_b32_saddr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: cluster_load_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV
+; GFX1250S-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-GISEL-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
%val = call i32 @llvm.amdgcn.cluster.load.b32.i32.p1(ptr addrspace(1) %gep, i32 22, i32 %mask)
@@ -66,17 +181,53 @@ entry:
}
define amdgpu_ps void @cluster_load_monitor_b32_saddr_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask, i32 %idx) {
-; GFX1250-LABEL: cluster_load_monitor_b32_saddr_scale_offset:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: cluster_load_b32 v2, v2, s[0:1] scale_offset th:TH_LOAD_BYPASS scope:SCOPE_SYS
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_monitor_b32_saddr_scale_offset:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: cluster_load_b32 v2, v2, s[0:1] scale_offset th:TH_LOAD_BYPASS scope:SCOPE_SYS
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_monitor_b32_saddr_scale_offset:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: cluster_load_b32 v2, v2, s[0:1] scale_offset th:TH_LOAD_BYPASS scope:SCOPE_SYS
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_monitor_b32_saddr_scale_offset:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_b32 v2, v2, s[0:1] scale_offset th:TH_LOAD_BYPASS scope:SCOPE_SYS
+; GFX1250S-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-SDAG-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_monitor_b32_saddr_scale_offset:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: cluster_load_b32 v2, v2, s[0:1] scale_offset th:TH_LOAD_BYPASS scope:SCOPE_SYS
+; GFX1250S-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-GISEL-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%idxprom = sext i32 %idx to i64
%gep = getelementptr i32, ptr addrspace(1) %addr, i64 %idxprom
@@ -86,18 +237,56 @@ entry:
}
define amdgpu_ps void @cluster_load_b64_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use, i32 %mask) {
-; GFX1250-LABEL: cluster_load_b64_vaddr:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_readfirstlane_b32 s0, v4
-; GFX1250-NEXT: s_mov_b32 m0, s0
-; GFX1250-NEXT: cluster_load_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_NT
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_b64_vaddr:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s0
+; GFX1250-SDAG-NEXT: cluster_load_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_NT
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: global_store_b64 v[2:3], v[0:1], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_b64_vaddr:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s0
+; GFX1250-GISEL-NEXT: cluster_load_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_NT
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: global_store_b64 v[2:3], v[0:1], off
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_b64_vaddr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_NT
+; GFX1250S-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-SDAG-NEXT: global_store_b64 v[2:3], v[0:1], off
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_b64_vaddr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s0
+; GFX1250S-GISEL-NEXT: cluster_load_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_NT
+; GFX1250S-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-GISEL-NEXT: global_store_b64 v[2:3], v[0:1], off
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
%val = call <2 x i32> @llvm.amdgcn.cluster.load.b64.v2i32.p1(ptr addrspace(1) %gep, i32 1, i32 %mask)
@@ -106,17 +295,53 @@ entry:
}
define amdgpu_ps void @cluster_load_b64_vaddr_imm_mask(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
-; GFX1250-LABEL: cluster_load_b64_vaddr_imm_mask:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: s_mov_b32 m0, 0x10007
-; GFX1250-NEXT: cluster_load_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b64 v[2:3], v[0:1], off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_b64_vaddr_imm_mask:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, 0x10007
+; GFX1250-SDAG-NEXT: cluster_load_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: global_store_b64 v[2:3], v[0:1], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_b64_vaddr_imm_mask:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, 0x10007
+; GFX1250-GISEL-NEXT: cluster_load_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: global_store_b64 v[2:3], v[0:1], off
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_b64_vaddr_imm_mask:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-SDAG-NEXT: global_store_b64 v[2:3], v[0:1], off
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_b64_vaddr_imm_mask:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, 0x10007
+; GFX1250S-GISEL-NEXT: cluster_load_b64 v[0:1], v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-GISEL-NEXT: global_store_b64 v[2:3], v[0:1], off
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
%val = call <2 x i32> @llvm.amdgcn.cluster.load.b64.v2i32.p1(ptr addrspace(1) %gep, i32 10, i32 65543)
@@ -125,18 +350,57 @@ entry:
}
define amdgpu_ps void @cluster_load_b64_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask) {
-; GFX1250-LABEL: cluster_load_b64_saddr:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_mov_b32_e32 v2, 0
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_b64_saddr:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_b64_saddr:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_b64_saddr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV
+; GFX1250S-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-SDAG-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_b64_saddr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_NT_HT scope:SCOPE_DEV
+; GFX1250S-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
%val = call <2 x i32> @llvm.amdgcn.cluster.load.b64.v2i32.p1(ptr addrspace(1) %gep, i32 22, i32 %mask)
@@ -145,17 +409,53 @@ entry:
}
define amdgpu_ps void @cluster_load_monitor_b64_saddr_scale_offset(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask, i32 %idx) {
-; GFX1250-LABEL: cluster_load_monitor_b64_saddr_scale_offset:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] scale_offset th:TH_LOAD_BYPASS scope:SCOPE_SYS
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_monitor_b64_saddr_scale_offset:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] scale_offset th:TH_LOAD_BYPASS scope:SCOPE_SYS
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_monitor_b64_saddr_scale_offset:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] scale_offset th:TH_LOAD_BYPASS scope:SCOPE_SYS
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_monitor_b64_saddr_scale_offset:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] scale_offset th:TH_LOAD_BYPASS scope:SCOPE_SYS
+; GFX1250S-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-SDAG-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_monitor_b64_saddr_scale_offset:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] scale_offset th:TH_LOAD_BYPASS scope:SCOPE_SYS
+; GFX1250S-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%idxprom = sext i32 %idx to i64
%gep = getelementptr i64, ptr addrspace(1) %addr, i64 %idxprom
@@ -165,18 +465,56 @@ entry:
}
define amdgpu_ps void @cluster_load_b128_vaddr(ptr addrspace(1) %addr, ptr addrspace(1) %use, i32 %mask) {
-; GFX1250-LABEL: cluster_load_b128_vaddr:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_readfirstlane_b32 s0, v4
-; GFX1250-NEXT: s_mov_b32 m0, s0
-; GFX1250-NEXT: cluster_load_b128 v[4:7], v[0:1], off offset:32 th:TH_LOAD_NT
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_b128_vaddr:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s0
+; GFX1250-SDAG-NEXT: cluster_load_b128 v[4:7], v[0:1], off offset:32 th:TH_LOAD_NT
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_b128_vaddr:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s0
+; GFX1250-GISEL-NEXT: cluster_load_b128 v[4:7], v[0:1], off offset:32 th:TH_LOAD_NT
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_b128_vaddr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_b128 v[4:7], v[0:1], off offset:32 th:TH_LOAD_NT
+; GFX1250S-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-SDAG-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_b128_vaddr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_readfirstlane_b32 s0, v4
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s0
+; GFX1250S-GISEL-NEXT: cluster_load_b128 v[4:7], v[0:1], off offset:32 th:TH_LOAD_NT
+; GFX1250S-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-GISEL-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
%val = call <4 x i32> @llvm.amdgcn.cluster.load.b128.v4i32.p1(ptr addrspace(1) %gep, i32 1, i32 %mask)
@@ -185,17 +523,53 @@ entry:
}
define amdgpu_ps void @cluster_load_b128_vaddr_imm_mask(ptr addrspace(1) %addr, ptr addrspace(1) %use) {
-; GFX1250-LABEL: cluster_load_b128_vaddr_imm_mask:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: s_mov_b32 m0, 15
-; GFX1250-NEXT: cluster_load_b128 v[4:7], v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b128 v[2:3], v[4:7], off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_b128_vaddr_imm_mask:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, 15
+; GFX1250-SDAG-NEXT: cluster_load_b128 v[4:7], v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_b128_vaddr_imm_mask:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, 15
+; GFX1250-GISEL-NEXT: cluster_load_b128 v[4:7], v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_b128_vaddr_imm_mask:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_b128 v[4:7], v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-SDAG-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_b128_vaddr_imm_mask:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, 15
+; GFX1250S-GISEL-NEXT: cluster_load_b128 v[4:7], v[0:1], off offset:32 th:TH_LOAD_HT scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-GISEL-NEXT: global_store_b128 v[2:3], v[4:7], off
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
%val = call <4 x i32> @llvm.amdgcn.cluster.load.b128.v4i32.p1(ptr addrspace(1) %gep, i32 10, i32 15)
@@ -204,18 +578,57 @@ entry:
}
define amdgpu_ps void @cluster_load_b128_saddr(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 inreg %mask) {
-; GFX1250-LABEL: cluster_load_b128_saddr:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_mov_b32_e32 v2, 0
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: cluster_load_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_BYPASS scope:SCOPE_SYS
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b128 v[0:1], v[2:5], off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_b128_saddr:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: cluster_load_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_BYPASS scope:SCOPE_SYS
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_b128_saddr:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: cluster_load_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_BYPASS scope:SCOPE_SYS
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_b128_saddr:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_BYPASS scope:SCOPE_SYS
+; GFX1250S-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_b128_saddr:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: cluster_load_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_BYPASS scope:SCOPE_SYS
+; GFX1250S-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
%val = call <4 x i32> @llvm.amdgcn.cluster.load.b128.v4i32.p1(ptr addrspace(1) %gep, i32 27, i32 inreg %mask)
@@ -223,19 +636,60 @@ entry:
ret void
}
define amdgpu_ps void @cluster_load_b32_saddr_vmask(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %mask) {
-; GFX1250-LABEL: cluster_load_b32_saddr_vmask:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_readfirstlane_b32 s2, v2
-; GFX1250-NEXT: v_mov_b32_e32 v2, 0
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: cluster_load_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_NT
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_b32_saddr_vmask:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: cluster_load_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_NT
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_b32_saddr_vmask:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: cluster_load_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_NT
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_b32_saddr_vmask:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_NT
+; GFX1250S-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-SDAG-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_b32_saddr_vmask:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250S-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: cluster_load_b32 v2, v2, s[0:1] offset:32 th:TH_LOAD_NT
+; GFX1250S-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-GISEL-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
%val = call i32 @llvm.amdgcn.cluster.load.b32.i32.p1(ptr addrspace(1) %gep, i32 1, i32 %mask)
@@ -244,19 +698,60 @@ entry:
}
define amdgpu_ps void @cluster_load_b64_saddr_vmask(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %mask) {
-; GFX1250-LABEL: cluster_load_b64_saddr_vmask:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_readfirstlane_b32 s2, v2
-; GFX1250-NEXT: v_mov_b32_e32 v2, 0
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_NT
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_b64_saddr_vmask:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_NT
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_b64_saddr_vmask:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_NT
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_b64_saddr_vmask:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_NT
+; GFX1250S-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-SDAG-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_b64_saddr_vmask:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250S-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: cluster_load_b64 v[2:3], v2, s[0:1] offset:32 th:TH_LOAD_NT
+; GFX1250S-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-GISEL-NEXT: global_store_b64 v[0:1], v[2:3], off
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
%val = call <2 x i32> @llvm.amdgcn.cluster.load.b64.v2i32.p1(ptr addrspace(1) %gep, i32 1, i32 %mask)
@@ -265,19 +760,60 @@ entry:
}
define amdgpu_ps void @cluster_load_b128_saddr_vmask(ptr addrspace(1) inreg %addr, ptr addrspace(1) %use, i32 %mask) {
-; GFX1250-LABEL: cluster_load_b128_saddr_vmask:
-; GFX1250: ; %bb.0: ; %entry
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-NEXT: v_readfirstlane_b32 s2, v2
-; GFX1250-NEXT: v_mov_b32_e32 v2, 0
-; GFX1250-NEXT: s_mov_b32 m0, s2
-; GFX1250-NEXT: cluster_load_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_NT
-; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: global_store_b128 v[0:1], v[2:5], off
-; GFX1250-NEXT: s_endpgm
+; GFX1250-SDAG-LABEL: cluster_load_b128_saddr_vmask:
+; GFX1250-SDAG: ; %bb.0: ; %entry
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-SDAG-NEXT: v_nop
+; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-SDAG-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-SDAG-NEXT: s_mov_b32 m0, s2
+; GFX1250-SDAG-NEXT: cluster_load_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_NT
+; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: cluster_load_b128_saddr_vmask:
+; GFX1250-GISEL: ; %bb.0: ; %entry
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-GISEL-NEXT: v_nop
+; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250-GISEL-NEXT: cluster_load_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_NT
+; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-GISEL-NEXT: s_endpgm
+;
+; GFX1250S-SDAG-LABEL: cluster_load_b128_saddr_vmask:
+; GFX1250S-SDAG: ; %bb.0: ; %entry
+; GFX1250S-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-SDAG-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-SDAG-NEXT: v_nop
+; GFX1250S-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-SDAG-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250S-SDAG-NEXT: s_mov_b32 m0, 0
+; GFX1250S-SDAG-NEXT: cluster_load_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_NT
+; GFX1250S-SDAG-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250S-SDAG-NEXT: s_endpgm
+;
+; GFX1250S-GISEL-LABEL: cluster_load_b128_saddr_vmask:
+; GFX1250S-GISEL: ; %bb.0: ; %entry
+; GFX1250S-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250S-GISEL-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250S-GISEL-NEXT: v_nop
+; GFX1250S-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250S-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250S-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX1250S-GISEL-NEXT: s_mov_b32 m0, s2
+; GFX1250S-GISEL-NEXT: cluster_load_b128 v[2:5], v2, s[0:1] offset:32 th:TH_LOAD_NT
+; GFX1250S-GISEL-NEXT: s_wait_loadcnt 0x0
+; GFX1250S-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250S-GISEL-NEXT: s_endpgm
entry:
%gep = getelementptr i64, ptr addrspace(1) %addr, i32 4
%val = call <4 x i32> @llvm.amdgcn.cluster.load.b128.v4i32.p1(ptr addrspace(1) %gep, i32 1, i32 %mask)
@@ -285,5 +821,4 @@ entry:
ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX1250-GISEL: {{.*}}
-; GFX1250-SDAG: {{.*}}
+; GFX1250: {{.*}}
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