[llvm] [CodeGen] Add New Pass Manager support for RA Basic and PBQP (PR #218975)
Nikhil Kotikalapudi via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 26 11:49:07 PDT 2026
https://github.com/nkotikal updated https://github.com/llvm/llvm-project/pull/218975
>From 636a71b27066f468f440057b42a19737a3789a63 Mon Sep 17 00:00:00 2001
From: nkotikal <nak00001 at outlook.com>
Date: Fri, 21 Aug 2026 11:01:29 -0400
Subject: [PATCH 1/3] temp pass commit
---
llvm/include/llvm/CodeGen/RegAllocBasic.h | 32 ++++++++++
llvm/include/llvm/CodeGen/RegAllocPBQP.h | 15 +++++
llvm/include/llvm/Passes/CodeGenPassBuilder.h | 8 +++
.../llvm/Passes/MachinePassRegistry.def | 4 +-
llvm/lib/CodeGen/RegAllocBasic.cpp | 62 +++++++++++++++----
llvm/lib/CodeGen/RegAllocBasic.h | 15 +++++
llvm/lib/CodeGen/RegAllocPBQP.cpp | 53 ++++++++++++----
llvm/lib/Passes/PassBuilder.cpp | 2 +
.../llc/new-pm/x86_64-regalloc-pipeline.mir | 4 ++
9 files changed, 169 insertions(+), 26 deletions(-)
create mode 100644 llvm/include/llvm/CodeGen/RegAllocBasic.h
diff --git a/llvm/include/llvm/CodeGen/RegAllocBasic.h b/llvm/include/llvm/CodeGen/RegAllocBasic.h
new file mode 100644
index 0000000000000..cfe54ca2a66af
--- /dev/null
+++ b/llvm/include/llvm/CodeGen/RegAllocBasic.h
@@ -0,0 +1,32 @@
+//==- RegAllocBasic.h ----------- basic register allocator ---------*-C++-*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_CODEGEN_REGALLOC_BASIC_H
+#define LLVM_CODEGEN_REGALLOC_BASIC_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+
+class RABasicPass : public RequiredPassInfoMixin<RABasicPass> {
+public:
+ LLVM_ABI PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+
+ MachineFunctionProperties getRequiredProperties() const {
+ return MachineFunctionProperties().setNoPHIs();
+ }
+
+ MachineFunctionProperties getClearedProperties() const {
+ return MachineFunctionProperties().setIsSSA();
+ }
+};
+
+} // namespace llvm
+
+#endif // LLVM_CODEGEN_REGALLOC_BASIC_H
diff --git a/llvm/include/llvm/CodeGen/RegAllocPBQP.h b/llvm/include/llvm/CodeGen/RegAllocPBQP.h
index a1a4c148fe73b..19a8545e9e9f7 100644
--- a/llvm/include/llvm/CodeGen/RegAllocPBQP.h
+++ b/llvm/include/llvm/CodeGen/RegAllocPBQP.h
@@ -17,6 +17,7 @@
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/Hashing.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/PBQP/CostAllocator.h"
#include "llvm/CodeGen/PBQP/Graph.h"
#include "llvm/CodeGen/PBQP/Math.h"
@@ -531,6 +532,20 @@ inline Solution solve(PBQPRAGraph& G) {
LLVM_ABI FunctionPass *
createPBQPRegisterAllocator(char *customPassID = nullptr);
+class RAPBQPPass : public RequiredPassInfoMixin<RAPBQPPass> {
+public:
+ LLVM_ABI PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+
+ MachineFunctionProperties getRequiredProperties() const {
+ return MachineFunctionProperties().setNoPHIs();
+ }
+
+ MachineFunctionProperties getClearedProperties() const {
+ return MachineFunctionProperties().setIsSSA();
+ }
+};
+
} // end namespace llvm
#endif // LLVM_CODEGEN_REGALLOCPBQP_H
diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
index 11e448dd7f78b..f48272f538bd1 100644
--- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h
+++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h
@@ -72,8 +72,10 @@
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/ProcessImplicitDefs.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
+#include "llvm/CodeGen/RegAllocBasic.h"
#include "llvm/CodeGen/RegAllocFast.h"
#include "llvm/CodeGen/RegAllocGreedyPass.h"
+#include "llvm/CodeGen/RegAllocPBQP.h"
#include "llvm/CodeGen/RegUsageInfoCollector.h"
#include "llvm/CodeGen/RegUsageInfoPropagate.h"
#include "llvm/CodeGen/RegisterCoalescerPass.h"
@@ -1182,6 +1184,12 @@ void CodeGenPassBuilder<Derived, TargetMachineT>::addRegAllocPass(
case RegAllocType::Greedy:
addMachineFunctionPass(RAGreedyPass(), PMW);
break;
+ case RegAllocType::Basic:
+ addMachineFunctionPass(RABasicPass(), PMW);
+ break;
+ case RegAllocType::PBQP:
+ addMachineFunctionPass(RAPBQPPass(), PMW);
+ break;
default:
reportFatalUsageError("register allocator not supported yet");
}
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index dae1be841d3d8..7a8d4899e9505 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -127,6 +127,8 @@ MACHINE_FUNCTION_PASS("print<slot-indexes>", SlotIndexesPrinterPass(errs()))
MACHINE_FUNCTION_PASS("print<virtregmap>", VirtRegMapPrinterPass(errs()))
MACHINE_FUNCTION_PASS("process-imp-defs", ProcessImplicitDefsPass())
MACHINE_FUNCTION_PASS("prolog-epilog", PrologEpilogInserterPass())
+MACHINE_FUNCTION_PASS("ra-basic", RABasicPass())
+MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass())
MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass())
MACHINE_FUNCTION_PASS("reg-usage-propagation", RegUsageInfoPropagationPass())
MACHINE_FUNCTION_PASS("register-coalescer", RegisterCoalescerPass())
@@ -250,8 +252,6 @@ DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitter
DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
DUMMY_MACHINE_FUNCTION_PASS("prolog-epilog-code", PrologEpilogCodeInserterPass)
-DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass)
-DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass)
DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass)
DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass)
DUMMY_MACHINE_FUNCTION_PASS("regbankselect", RegBankSelectPass)
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp
index 0d8a6970b41e7..f67daf22c503e 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.cpp
+++ b/llvm/lib/CodeGen/RegAllocBasic.cpp
@@ -24,8 +24,11 @@
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/RegAllocBasic.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
+#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/Pass.h"
#include "llvm/Support/Debug.h"
@@ -218,24 +221,29 @@ MCRegister RABasic::selectOrSplit(const LiveInterval &VirtReg,
}
bool RABasic::runOnMachineFunction(MachineFunction &mf) {
+ return run(mf, getAnalysis<VirtRegMapWrapperLegacy>().getVRM(),
+ getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
+ getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM(),
+ getAnalysis<LiveStacksWrapperLegacy>().getLS(),
+ getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI(),
+ getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree(),
+ getAnalysis<MachineLoopInfoWrapperPass>().getLI(),
+ &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI());
+}
+
+bool RABasic::run(MachineFunction &mf, VirtRegMap &VRMRef, LiveIntervals &LISRef,
+ LiveRegMatrix &LRMRef, LiveStacks &LSS,
+ MachineBlockFrequencyInfo &MBFI, MachineDominatorTree &MDT,
+ MachineLoopInfo &Loops, ProfileSummaryInfo *PSI) {
LLVM_DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
<< "********** Function: " << mf.getName() << '\n');
MF = &mf;
- auto &MBFI = getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
- auto &LiveStks = getAnalysis<LiveStacksWrapperLegacy>().getLS();
- auto &MDT = getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
-
- RegAllocBase::init(getAnalysis<VirtRegMapWrapperLegacy>().getVRM(),
- getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
- getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM());
- VirtRegAuxInfo VRAI(*MF, *LIS, *VRM,
- getAnalysis<MachineLoopInfoWrapperPass>().getLI(), MBFI,
- &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI());
+ RegAllocBase::init(VRMRef, LISRef, LRMRef);
+ VirtRegAuxInfo VRAI(*MF, *LIS, *VRM, Loops, MBFI, PSI);
VRAI.calculateSpillWeightsAndHints();
- SpillerInstance.reset(
- createInlineSpiller({*LIS, LiveStks, MDT, MBFI}, *MF, *VRM, VRAI));
+ SpillerInstance.reset(createInlineSpiller({*LIS, LSS, MDT, MBFI}, *MF, *VRM, VRAI));
allocatePhysRegs();
postOptimization();
@@ -247,6 +255,36 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
return true;
}
+PreservedAnalyses RABasicPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ MFPropsModifier _(*this, MF);
+
+ auto &MAMProxy = MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(MF);
+ ProfileSummaryInfo *PSI = MAMProxy.getCachedResult<ProfileSummaryAnalysis>(
+ *MF.getFunction().getParent());
+
+ RABasic Impl;
+ bool Changed =
+ Impl.run(MF, MFAM.getResult<VirtRegMapAnalysis>(MF),
+ MFAM.getResult<LiveIntervalsAnalysis>(MF),
+ MFAM.getResult<LiveRegMatrixAnalysis>(MF),
+ MFAM.getResult<LiveStacksAnalysis>(MF),
+ MFAM.getResult<MachineBlockFrequencyAnalysis>(MF),
+ MFAM.getResult<MachineDominatorTreeAnalysis>(MF),
+ MFAM.getResult<MachineLoopAnalysis>(MF), PSI);
+ if (!Changed)
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<LiveIntervalsAnalysis>();
+ PA.preserve<SlotIndexesAnalysis>();
+ PA.preserve<LiveDebugVariablesAnalysis>();
+ PA.preserve<LiveStacksAnalysis>();
+ PA.preserve<VirtRegMapAnalysis>();
+ PA.preserve<LiveRegMatrixAnalysis>();
+ return PA;
+}
+
FunctionPass* llvm::createBasicRegisterAllocator() {
return new RABasic();
}
diff --git a/llvm/lib/CodeGen/RegAllocBasic.h b/llvm/lib/CodeGen/RegAllocBasic.h
index a296c90ef78f8..36a3548d32b75 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.h
+++ b/llvm/lib/CodeGen/RegAllocBasic.h
@@ -24,6 +24,15 @@
namespace llvm {
+class LiveIntervals;
+class LiveRegMatrix;
+class LiveStacks;
+class MachineBlockFrequencyInfo;
+class MachineDominatorTree;
+class MachineLoopInfo;
+class ProfileSummaryInfo;
+class VirtRegMap;
+
struct CompSpillWeight {
bool operator()(const LiveInterval *A, const LiveInterval *B) const {
// Compare by weight first, then use register number as a stable tie-breaker
@@ -86,6 +95,12 @@ class LLVM_LIBRARY_VISIBILITY RABasic : public MachineFunctionPass,
/// Perform register allocation.
bool runOnMachineFunction(MachineFunction &mf) override;
+ /// Shared implementation used by the legacy and new pass managers.
+ bool run(MachineFunction &MF, VirtRegMap &VRM, LiveIntervals &LIS,
+ LiveRegMatrix &LRM, LiveStacks &LSS,
+ MachineBlockFrequencyInfo &MBFI, MachineDominatorTree &MDT,
+ MachineLoopInfo &Loops, ProfileSummaryInfo *PSI);
+
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
MachineFunctionProperties::Property::NoPHIs);
diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp
index 0650692962efa..59d9c3a920382 100644
--- a/llvm/lib/CodeGen/RegAllocPBQP.cpp
+++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp
@@ -50,6 +50,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/PBQP/Graph.h"
#include "llvm/CodeGen/PBQP/Math.h"
@@ -129,6 +130,11 @@ class RegAllocPBQP : public MachineFunctionPass {
/// Perform register allocation
bool runOnMachineFunction(MachineFunction &MF) override;
+ /// Shared implementation used by the legacy and new pass managers.
+ bool run(MachineFunction &MF, LiveIntervals &LIS,
+ MachineBlockFrequencyInfo &MBFI, LiveStacks &LiveStks,
+ MachineDominatorTree &MDT, MachineLoopInfo &Loops, VirtRegMap &VRM);
+
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().setNoPHIs();
}
@@ -781,25 +787,26 @@ void RegAllocPBQP::postOptimization(Spiller &VRegSpiller, LiveIntervals &LIS) {
}
bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
- LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
- MachineBlockFrequencyInfo &MBFI =
- getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
-
- auto &LiveStks = getAnalysis<LiveStacksWrapperLegacy>().getLS();
- auto &MDT = getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
-
- VirtRegMap &VRM = getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
+ return run(MF, getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
+ getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI(),
+ getAnalysis<LiveStacksWrapperLegacy>().getLS(),
+ getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree(),
+ getAnalysis<MachineLoopInfoWrapperPass>().getLI(),
+ getAnalysis<VirtRegMapWrapperLegacy>().getVRM());
+}
- PBQPVirtRegAuxInfo VRAI(
- MF, LIS, VRM, getAnalysis<MachineLoopInfoWrapperPass>().getLI(), MBFI);
+bool RegAllocPBQP::run(MachineFunction &MF, LiveIntervals &LIS,
+ MachineBlockFrequencyInfo &MBFI, LiveStacks &LiveStks,
+ MachineDominatorTree &MDT, MachineLoopInfo &Loops,
+ VirtRegMap &VRM) {
+ PBQPVirtRegAuxInfo VRAI(MF, LIS, VRM, Loops, MBFI);
VRAI.calculateSpillWeightsAndHints();
// FIXME: we create DefaultVRAI here to match existing behavior pre-passing
// the VRAI through the spiller to the live range editor. However, it probably
// makes more sense to pass the PBQP VRAI. The existing behavior had
// LiveRangeEdit make its own VirtRegAuxInfo object.
- VirtRegAuxInfo DefaultVRAI(
- MF, LIS, VRM, getAnalysis<MachineLoopInfoWrapperPass>().getLI(), MBFI);
+ VirtRegAuxInfo DefaultVRAI(MF, LIS, VRM, Loops, MBFI);
std::unique_ptr<Spiller> VRegSpiller(
createInlineSpiller({LIS, LiveStks, MDT, MBFI}, MF, VRM, DefaultVRAI));
@@ -878,6 +885,28 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
return true;
}
+PreservedAnalyses RAPBQPPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ MFPropsModifier _(*this, MF);
+
+ RegAllocPBQP Impl;
+ bool Changed = Impl.run(MF, MFAM.getResult<LiveIntervalsAnalysis>(MF),
+ MFAM.getResult<MachineBlockFrequencyAnalysis>(MF),
+ MFAM.getResult<LiveStacksAnalysis>(MF),
+ MFAM.getResult<MachineDominatorTreeAnalysis>(MF),
+ MFAM.getResult<MachineLoopAnalysis>(MF),
+ MFAM.getResult<VirtRegMapAnalysis>(MF));
+ if (!Changed)
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<LiveIntervalsAnalysis>();
+ PA.preserve<SlotIndexesAnalysis>();
+ PA.preserve<LiveStacksAnalysis>();
+ PA.preserve<VirtRegMapAnalysis>();
+ return PA;
+}
+
/// Create Printable object for node and register info.
static Printable PrintNodeInfo(PBQP::RegAlloc::PBQPRAGraph::NodeId NId,
const PBQP::RegAlloc::PBQPRAGraph &G) {
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 665ce27788d6f..e345734bd3664 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -161,8 +161,10 @@
#include "llvm/CodeGen/ProcessImplicitDefs.h"
#include "llvm/CodeGen/ReachingDefAnalysis.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
+#include "llvm/CodeGen/RegAllocBasic.h"
#include "llvm/CodeGen/RegAllocFast.h"
#include "llvm/CodeGen/RegAllocGreedyPass.h"
+#include "llvm/CodeGen/RegAllocPBQP.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegUsageInfoCollector.h"
#include "llvm/CodeGen/RegUsageInfoPropagate.h"
diff --git a/llvm/test/tools/llc/new-pm/x86_64-regalloc-pipeline.mir b/llvm/test/tools/llc/new-pm/x86_64-regalloc-pipeline.mir
index 7a50bcaf212c7..6cdc16d68dd4a 100644
--- a/llvm/test/tools/llc/new-pm/x86_64-regalloc-pipeline.mir
+++ b/llvm/test/tools/llc/new-pm/x86_64-regalloc-pipeline.mir
@@ -1,6 +1,10 @@
# REQUIRES: x86-registered-target
# RUN: llc -mtriple=x86_64-unknown-linux-gnu -enable-new-pm -O3 -regalloc-npm=fast -print-pipeline-passes %s -o - 2>&1 | FileCheck %s
# RUN: llc -mtriple=x86_64-unknown-linux-gnu -enable-new-pm -O3 -regalloc-npm=greedy -print-pipeline-passes %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-GREEDY
+# RUN: llc -mtriple=x86_64-unknown-linux-gnu -enable-new-pm -O3 -regalloc-npm=basic -print-pipeline-passes %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-BASIC
+# RUN: llc -mtriple=x86_64-unknown-linux-gnu -enable-new-pm -O3 -regalloc-npm=pbqp -print-pipeline-passes %s -o - 2>&1 | FileCheck %s --check-prefix=CHECK-PBQP
# CHECK: regallocfast
# CHECK-GREEDY: greedy<all>
+# CHECK-BASIC: ra-basic
+# CHECK-PBQP: ra-pbqp
>From 819070668831fe280f96eaba69fda2a790ffccea Mon Sep 17 00:00:00 2001
From: nkotikal <nak00001 at outlook.com>
Date: Wed, 26 Aug 2026 03:03:55 -0400
Subject: [PATCH 2/3] added options struct for ra basic and made ra basic
possible with npm on amdgpu
---
llvm/include/llvm/CodeGen/RegAllocBasic.h | 13 +++++++++++
llvm/lib/CodeGen/RegAllocBasic.cpp | 2 +-
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 23 ++++++++++++++-----
.../llc/new-pm/regalloc-amdgpu-npm-compile.ll | 11 +++++++++
.../test/tools/llc/new-pm/regalloc-amdgpu.mir | 7 ++++--
.../tools/llc/new-pm/regalloc-npm-compile.ll | 9 ++++++++
6 files changed, 56 insertions(+), 9 deletions(-)
create mode 100644 llvm/test/tools/llc/new-pm/regalloc-amdgpu-npm-compile.ll
create mode 100644 llvm/test/tools/llc/new-pm/regalloc-npm-compile.ll
diff --git a/llvm/include/llvm/CodeGen/RegAllocBasic.h b/llvm/include/llvm/CodeGen/RegAllocBasic.h
index cfe54ca2a66af..180465f1de031 100644
--- a/llvm/include/llvm/CodeGen/RegAllocBasic.h
+++ b/llvm/include/llvm/CodeGen/RegAllocBasic.h
@@ -10,11 +10,21 @@
#define LLVM_CODEGEN_REGALLOC_BASIC_H
#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/CodeGen/RegAllocCommon.h"
namespace llvm {
class RABasicPass : public RequiredPassInfoMixin<RABasicPass> {
public:
+ struct Options {
+ RegAllocFilterFunc Filter;
+ StringRef FilterName;
+ Options(RegAllocFilterFunc F = nullptr, StringRef FN = "all")
+ : Filter(std::move(F)), FilterName(FN) {}
+ };
+
+ RABasicPass(Options Opts = Options()) : Opts(std::move(Opts)) {}
+
LLVM_ABI PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
@@ -25,6 +35,9 @@ class RABasicPass : public RequiredPassInfoMixin<RABasicPass> {
MachineFunctionProperties getClearedProperties() const {
return MachineFunctionProperties().setIsSSA();
}
+
+private:
+ Options Opts;
};
} // namespace llvm
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp
index f67daf22c503e..ef9e2471ec2bd 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.cpp
+++ b/llvm/lib/CodeGen/RegAllocBasic.cpp
@@ -263,7 +263,7 @@ PreservedAnalyses RABasicPass::run(MachineFunction &MF,
ProfileSummaryInfo *PSI = MAMProxy.getCachedResult<ProfileSummaryAnalysis>(
*MF.getFunction().getParent());
- RABasic Impl;
+ RABasic Impl(Opts.Filter);
bool Changed =
Impl.run(MF, MFAM.getResult<VirtRegMapAnalysis>(MF),
MFAM.getResult<LiveIntervalsAnalysis>(MF),
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 6f0b06eaf95bb..6ba852d26dc8c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -269,13 +269,12 @@ static cl::opt<RegAllocType, false, RegAllocTypeParser> WWMRegAllocNPM(
cl::desc("Register allocator for WWM registers (new pass manager)"));
/// Check if the given RegAllocType is supported for AMDGPU NPM register
-/// allocation. Only Fast and Greedy are supported; Basic and PBQP are not.
+/// allocation. Fast, Greedy, and Basic are supported; PBQP is not.
static Error checkRegAllocSupported(RegAllocType RAType, StringRef RegName) {
- if (RAType == RegAllocType::Basic || RAType == RegAllocType::PBQP) {
+ if (RAType == RegAllocType::PBQP) {
return make_error<StringError>(
- Twine("unsupported register allocator '") +
- (RAType == RegAllocType::Basic ? "basic" : "pbqp") + "' for " +
- RegName + " registers",
+ Twine("unsupported register allocator 'pbqp' for ") + RegName +
+ " registers",
inconvertibleErrorCode());
}
return Error::success();
@@ -301,7 +300,7 @@ Error AMDGPUCodeGenPassBuilder::validateRegAllocOptions() const {
inconvertibleErrorCode());
}
- // 3. Only Fast and Greedy allocators are supported for AMDGPU.
+ // 3. Only Fast, Greedy, and Basic allocators are supported for AMDGPU.
if (auto Err = checkRegAllocSupported(SGPRRegAllocNPM, "SGPR"))
return Err;
if (auto Err = checkRegAllocSupported(WWMRegAllocNPM, "WWM"))
@@ -2562,6 +2561,8 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignAndRewriteFast(
// SGPR allocation - default to fast at -O0.
if (SGPRRegAllocNPM == RegAllocType::Greedy)
addMachineFunctionPass(RAGreedyPass({onlyAllocateSGPRs, "sgpr"}), PMW);
+ else if (SGPRRegAllocNPM == RegAllocType::Basic)
+ addMachineFunctionPass(RABasicPass({onlyAllocateSGPRs, "sgpr"}), PMW);
else
addMachineFunctionPass(RegAllocFastPass({onlyAllocateSGPRs, "sgpr", false}),
PMW);
@@ -2575,6 +2576,8 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignAndRewriteFast(
// WWM allocation - default to fast at -O0.
if (WWMRegAllocNPM == RegAllocType::Greedy)
addMachineFunctionPass(RAGreedyPass({onlyAllocateWWMRegs, "wwm"}), PMW);
+ else if (WWMRegAllocNPM == RegAllocType::Basic)
+ addMachineFunctionPass(RABasicPass({onlyAllocateWWMRegs, "wwm"}), PMW);
else
addMachineFunctionPass(
RegAllocFastPass({onlyAllocateWWMRegs, "wwm", false}), PMW);
@@ -2585,6 +2588,8 @@ Error AMDGPUCodeGenPassBuilder::addRegAssignAndRewriteFast(
// VGPR allocation - default to fast at -O0.
if (VGPRRegAllocNPM == RegAllocType::Greedy)
addMachineFunctionPass(RAGreedyPass({onlyAllocateVGPRs, "vgpr"}), PMW);
+ else if (VGPRRegAllocNPM == RegAllocType::Basic)
+ addMachineFunctionPass(RABasicPass({onlyAllocateVGPRs, "vgpr"}), PMW);
else
addMachineFunctionPass(RegAllocFastPass({onlyAllocateVGPRs, "vgpr"}), PMW);
@@ -2646,6 +2651,8 @@ Expected<bool> AMDGPUCodeGenPassBuilder::addRegAssignAndRewriteOptimized(
if (SGPRRegAllocNPM == RegAllocType::Fast)
addMachineFunctionPass(RegAllocFastPass({onlyAllocateSGPRs, "sgpr", false}),
PMW);
+ else if (SGPRRegAllocNPM == RegAllocType::Basic)
+ addMachineFunctionPass(RABasicPass({onlyAllocateSGPRs, "sgpr"}), PMW);
else
addMachineFunctionPass(RAGreedyPass({onlyAllocateSGPRs, "sgpr"}), PMW);
@@ -2670,6 +2677,8 @@ Expected<bool> AMDGPUCodeGenPassBuilder::addRegAssignAndRewriteOptimized(
if (WWMRegAllocNPM == RegAllocType::Fast)
addMachineFunctionPass(
RegAllocFastPass({onlyAllocateWWMRegs, "wwm", false}), PMW);
+ else if (WWMRegAllocNPM == RegAllocType::Basic)
+ addMachineFunctionPass(RABasicPass({onlyAllocateWWMRegs, "wwm"}), PMW);
else
addMachineFunctionPass(RAGreedyPass({onlyAllocateWWMRegs, "wwm"}), PMW);
addMachineFunctionPass(SILowerWWMCopiesPass(), PMW);
@@ -2679,6 +2688,8 @@ Expected<bool> AMDGPUCodeGenPassBuilder::addRegAssignAndRewriteOptimized(
// VGPR allocation - default to greedy at -O1 and above.
if (VGPRRegAllocNPM == RegAllocType::Fast)
addMachineFunctionPass(RegAllocFastPass({onlyAllocateVGPRs, "vgpr"}), PMW);
+ else if (VGPRRegAllocNPM == RegAllocType::Basic)
+ addMachineFunctionPass(RABasicPass({onlyAllocateVGPRs, "vgpr"}), PMW);
else
addMachineFunctionPass(RAGreedyPass({onlyAllocateVGPRs, "vgpr"}), PMW);
diff --git a/llvm/test/tools/llc/new-pm/regalloc-amdgpu-npm-compile.ll b/llvm/test/tools/llc/new-pm/regalloc-amdgpu-npm-compile.ll
new file mode 100644
index 0000000000000..386c3b14d0792
--- /dev/null
+++ b/llvm/test/tools/llc/new-pm/regalloc-amdgpu-npm-compile.ll
@@ -0,0 +1,11 @@
+; REQUIRES: amdgpu-registered-target
+; RUN: llc -verify-machineinstrs -enable-new-pm -O3 -sgpr-regalloc-npm=basic -wwm-regalloc-npm=basic -vgpr-regalloc-npm=basic -mtriple=amdgpu7.00-amd-amdhsa -filetype=null %s
+
+declare void @bar()
+
+; Exercise SGPR allocation with basic NPM register allocators.
+define void @foo() {
+ call void asm sideeffect "; clobber", "~{s33}"()
+ call void @bar()
+ ret void
+}
diff --git a/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir b/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
index 9823983f0f0bb..5fa899d3bf3c8 100644
--- a/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
+++ b/llvm/test/tools/llc/new-pm/regalloc-amdgpu.mir
@@ -13,8 +13,10 @@
# RUN: llc -mtriple=amdgcn -enable-new-pm -O3 -sgpr-regalloc-npm=greedy -wwm-regalloc-npm=greedy -vgpr-regalloc-npm=greedy -print-pipeline-passes -filetype=null %s 2>&1 | FileCheck %s --check-prefix=NPM-GREEDY
# RUN: llc -mtriple=amdgcn -enable-new-pm -O3 -sgpr-regalloc-npm=fast -print-pipeline-passes -filetype=null %s 2>&1 | FileCheck %s --check-prefix=NPM-MIXED
+# Test basic allocator with AMDGPU-specific NPM regalloc options
+# RUN: llc -mtriple=amdgcn -enable-new-pm -O3 -sgpr-regalloc-npm=basic -wwm-regalloc-npm=basic -vgpr-regalloc-npm=basic -print-pipeline-passes -filetype=null %s 2>&1 | FileCheck %s --check-prefix=NPM-BASIC
+
# Test error cases for unsupported allocators
-# RUN: not llc -mtriple=amdgcn -enable-new-pm -sgpr-regalloc-npm=basic -filetype=null %s 2>&1 | FileCheck %s --check-prefix=ERR-BASIC
# RUN: not llc -mtriple=amdgcn -enable-new-pm -vgpr-regalloc-npm=pbqp -filetype=null %s 2>&1 | FileCheck %s --check-prefix=ERR-PBQP
# Test error when legacy PM options are used with NPM
@@ -52,8 +54,9 @@
# NPM-MIXED: greedy<wwm>
# NPM-MIXED: greedy<vgpr>
+# NPM-BASIC: ra-basic
+
# Error messages for unsupported allocators.
-# ERR-BASIC: unsupported register allocator 'basic' for SGPR registers
# ERR-PBQP: unsupported register allocator 'pbqp' for VGPR registers
# Error message for legacy PM options with NPM.
diff --git a/llvm/test/tools/llc/new-pm/regalloc-npm-compile.ll b/llvm/test/tools/llc/new-pm/regalloc-npm-compile.ll
new file mode 100644
index 0000000000000..f82d91d58caa5
--- /dev/null
+++ b/llvm/test/tools/llc/new-pm/regalloc-npm-compile.ll
@@ -0,0 +1,9 @@
+; REQUIRES: x86-registered-target
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -enable-new-pm -O3 -regalloc-npm=basic -verify-machineinstrs -filetype=null %s
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu -enable-new-pm -O3 -regalloc-npm=pbqp -verify-machineinstrs -filetype=null %s
+
+define i32 @add(i32 %a, i32 %b) {
+entry:
+ %sum = add i32 %a, %b
+ ret i32 %sum
+}
>From 4e3d944acb67b42bf49db220dcdfec0974c44a23 Mon Sep 17 00:00:00 2001
From: nkotikal <nak00001 at outlook.com>
Date: Wed, 26 Aug 2026 12:26:51 -0400
Subject: [PATCH 3/3] clang format
---
llvm/lib/CodeGen/RegAllocBasic.cpp | 25 +++++++++++++------------
llvm/lib/CodeGen/RegAllocBasic.h | 6 +++---
llvm/lib/Passes/PassBuilder.cpp | 2 +-
3 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp
index ef9e2471ec2bd..9fa7c4ce3cfdf 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.cpp
+++ b/llvm/lib/CodeGen/RegAllocBasic.cpp
@@ -231,8 +231,8 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
&getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI());
}
-bool RABasic::run(MachineFunction &mf, VirtRegMap &VRMRef, LiveIntervals &LISRef,
- LiveRegMatrix &LRMRef, LiveStacks &LSS,
+bool RABasic::run(MachineFunction &mf, VirtRegMap &VRMRef,
+ LiveIntervals &LISRef, LiveRegMatrix &LRMRef, LiveStacks &LSS,
MachineBlockFrequencyInfo &MBFI, MachineDominatorTree &MDT,
MachineLoopInfo &Loops, ProfileSummaryInfo *PSI) {
LLVM_DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n"
@@ -243,7 +243,8 @@ bool RABasic::run(MachineFunction &mf, VirtRegMap &VRMRef, LiveIntervals &LISRef
VirtRegAuxInfo VRAI(*MF, *LIS, *VRM, Loops, MBFI, PSI);
VRAI.calculateSpillWeightsAndHints();
- SpillerInstance.reset(createInlineSpiller({*LIS, LSS, MDT, MBFI}, *MF, *VRM, VRAI));
+ SpillerInstance.reset(
+ createInlineSpiller({*LIS, LSS, MDT, MBFI}, *MF, *VRM, VRAI));
allocatePhysRegs();
postOptimization();
@@ -259,19 +260,19 @@ PreservedAnalyses RABasicPass::run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM) {
MFPropsModifier _(*this, MF);
- auto &MAMProxy = MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(MF);
+ auto &MAMProxy =
+ MFAM.getResult<ModuleAnalysisManagerMachineFunctionProxy>(MF);
ProfileSummaryInfo *PSI = MAMProxy.getCachedResult<ProfileSummaryAnalysis>(
*MF.getFunction().getParent());
RABasic Impl(Opts.Filter);
- bool Changed =
- Impl.run(MF, MFAM.getResult<VirtRegMapAnalysis>(MF),
- MFAM.getResult<LiveIntervalsAnalysis>(MF),
- MFAM.getResult<LiveRegMatrixAnalysis>(MF),
- MFAM.getResult<LiveStacksAnalysis>(MF),
- MFAM.getResult<MachineBlockFrequencyAnalysis>(MF),
- MFAM.getResult<MachineDominatorTreeAnalysis>(MF),
- MFAM.getResult<MachineLoopAnalysis>(MF), PSI);
+ bool Changed = Impl.run(MF, MFAM.getResult<VirtRegMapAnalysis>(MF),
+ MFAM.getResult<LiveIntervalsAnalysis>(MF),
+ MFAM.getResult<LiveRegMatrixAnalysis>(MF),
+ MFAM.getResult<LiveStacksAnalysis>(MF),
+ MFAM.getResult<MachineBlockFrequencyAnalysis>(MF),
+ MFAM.getResult<MachineDominatorTreeAnalysis>(MF),
+ MFAM.getResult<MachineLoopAnalysis>(MF), PSI);
if (!Changed)
return PreservedAnalyses::all();
auto PA = getMachineFunctionPassPreservedAnalyses();
diff --git a/llvm/lib/CodeGen/RegAllocBasic.h b/llvm/lib/CodeGen/RegAllocBasic.h
index 36a3548d32b75..55d4eca181860 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.h
+++ b/llvm/lib/CodeGen/RegAllocBasic.h
@@ -97,9 +97,9 @@ class LLVM_LIBRARY_VISIBILITY RABasic : public MachineFunctionPass,
/// Shared implementation used by the legacy and new pass managers.
bool run(MachineFunction &MF, VirtRegMap &VRM, LiveIntervals &LIS,
- LiveRegMatrix &LRM, LiveStacks &LSS,
- MachineBlockFrequencyInfo &MBFI, MachineDominatorTree &MDT,
- MachineLoopInfo &Loops, ProfileSummaryInfo *PSI);
+ LiveRegMatrix &LRM, LiveStacks &LSS, MachineBlockFrequencyInfo &MBFI,
+ MachineDominatorTree &MDT, MachineLoopInfo &Loops,
+ ProfileSummaryInfo *PSI);
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index 92c2f941cabb7..fc42bd3bdb615 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -171,8 +171,8 @@
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/ProcessImplicitDefs.h"
#include "llvm/CodeGen/ReachingDefAnalysis.h"
-#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
#include "llvm/CodeGen/RegAllocBasic.h"
+#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
#include "llvm/CodeGen/RegAllocFast.h"
#include "llvm/CodeGen/RegAllocGreedyPass.h"
#include "llvm/CodeGen/RegAllocPBQP.h"
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