[llvm] [VPlan][RISCV] Perform a simple version of LSR for EVL tail folded loops (PR #218987)

[Luke Lau via llvm-commits]

lukel97 wrote:

> I'm not that familiar with LSR but I'd imagine that's not the path to take. What if someone comes with an ISA extension to fold address computation into memory op? Would we want to have fixes in two LSRs then (or rather TTI for the regular and fixes in this new one)? Note that codegen folks wouldn't even know about this one.

The relevant hook is TTI.isLegalAddressingMode. That's what LSR already calls and we could plug it into this PR, but I omitted it for now since it will always be false for RISC-V.

https://github.com/llvm/llvm-project/pull/218987