[llvm] [NVPTX] Rewrite sm_110* to sm_101* as demanded by PTX version (PR #218968)
Alex MacLean via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 26 08:54:14 PDT 2026
https://github.com/AlexMaclean created https://github.com/llvm/llvm-project/pull/218968
None
>From a5a924b49abb52e8da38b9979597f5c5cb4ac27b Mon Sep 17 00:00:00 2001
From: Alex Maclean <amaclean at nvidia.com>
Date: Wed, 26 Aug 2026 08:51:56 -0700
Subject: [PATCH] [NVPTX] Rewrite sm_110* to sm_101* as demanded by PTX version
---
llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp | 30 ++++++++++++++--
llvm/lib/Target/NVPTX/NVPTXSubtarget.h | 2 +-
llvm/test/CodeGen/NVPTX/sm-110-rename.ll | 44 ++++++++++++++++++++++++
llvm/test/CodeGen/NVPTX/sm-version.ll | 14 ++++----
4 files changed, 80 insertions(+), 10 deletions(-)
create mode 100644 llvm/test/CodeGen/NVPTX/sm-110-rename.ll
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
index d271ea1710f05..e2048b721f6dd 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.cpp
@@ -45,6 +45,11 @@ void NVPTXSubtarget::anchor() {}
// Note: LLVM's minimum supported PTX version is 3.2 (see FeaturePTX in
// NVPTX.td), so older SMs that supported earlier PTX versions instead use 3.2
// as their effective minimum.
+//
+// Note: the sm_110 architectures are older than the table's PTX 9.0 row
+// suggests, because 9.0 is where they were renamed rather than introduced. They
+// take the minimum of the sm_101 names they were renamed from; see
+// getTargetName below.
static unsigned minPTXVersion(NVPTX::GPUKind Arch) {
switch (Arch) {
case NVPTX::GK_NONE:
@@ -87,6 +92,8 @@ static unsigned minPTXVersion(NVPTX::GPUKind Arch) {
case NVPTX::GK_SM_100a:
case NVPTX::GK_SM_101:
case NVPTX::GK_SM_101a:
+ case NVPTX::GK_SM_110:
+ case NVPTX::GK_SM_110a:
return 86;
case NVPTX::GK_SM_120:
case NVPTX::GK_SM_120a:
@@ -96,15 +103,13 @@ static unsigned minPTXVersion(NVPTX::GPUKind Arch) {
case NVPTX::GK_SM_103:
case NVPTX::GK_SM_103f:
case NVPTX::GK_SM_103a:
+ case NVPTX::GK_SM_110f:
case NVPTX::GK_SM_120f:
case NVPTX::GK_SM_121:
case NVPTX::GK_SM_121f:
case NVPTX::GK_SM_121a:
return 88;
case NVPTX::GK_SM_88:
- case NVPTX::GK_SM_110:
- case NVPTX::GK_SM_110f:
- case NVPTX::GK_SM_110a:
return 90;
case NVPTX::GK_SM_107:
case NVPTX::GK_SM_107f:
@@ -114,6 +119,25 @@ static unsigned minPTXVersion(NVPTX::GPUKind Arch) {
llvm_unreachable("invalid NVPTX GPUKind");
}
+StringRef NVPTXSubtarget::getTargetName() const {
+ // Prior to PTX ISA 9.0, The sm_110* targets were spelled as sm_101*. For
+ // backwards compatibility with older PTX, we rewrite the names to the old
+ // spelling as required by the PTX version.
+ if (!hasFeature(NVPTX::PTX90))
+ switch (Arch) {
+ case NVPTX::GK_SM_110:
+ return "sm_101";
+ case NVPTX::GK_SM_110f:
+ return "sm_101f";
+ case NVPTX::GK_SM_110a:
+ return "sm_101a";
+ default:
+ break;
+ }
+
+ return NVPTX::getArchName(Arch);
+}
+
NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef FS) {
// If the user did not provide a target we default to the `sm_75` target.
diff --git a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
index b2f24c1d5d2b3..0d1d64cf73b83 100644
--- a/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
+++ b/llvm/lib/Target/NVPTX/NVPTXSubtarget.h
@@ -198,7 +198,7 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo {
bool hasTargetName() const { return !getCPU().empty(); }
// The architecture's name, which is what `.target` is emitted from.
- StringRef getTargetName() const { return NVPTX::getArchName(Arch); }
+ StringRef getTargetName() const;
bool hasNativeBF16Support(unsigned Opcode) const;
diff --git a/llvm/test/CodeGen/NVPTX/sm-110-rename.ll b/llvm/test/CodeGen/NVPTX/sm-110-rename.ll
new file mode 100644
index 0000000000000..09cb7390c54f7
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/sm-110-rename.ll
@@ -0,0 +1,44 @@
+; PTX ISA 9.0 renamed sm_101, sm_101f and sm_101a to sm_110, sm_110f and
+; sm_110a. Naming one of these architectures with -mcpu emits `.target` with the
+; spelling the PTX version in use knows, so that the sm_110 names work on the PTX
+; versions predating the rename.
+
+; RUN: llc < %s -mcpu=sm_110 | FileCheck %s --check-prefix=SM101
+; RUN: llc < %s -mcpu=sm_110 -mattr=+ptx88 | FileCheck %s --check-prefix=SM101-PTX88
+; RUN: llc < %s -mcpu=sm_110 -mattr=+ptx90 | FileCheck %s --check-prefix=SM110
+
+; RUN: llc < %s -mcpu=sm_110f | FileCheck %s --check-prefix=SM101F
+; RUN: llc < %s -mcpu=sm_110f -mattr=+ptx90 | FileCheck %s --check-prefix=SM110F
+
+; RUN: llc < %s -mcpu=sm_110a | FileCheck %s --check-prefix=SM101A
+; RUN: llc < %s -mcpu=sm_110a -mattr=+ptx90 | FileCheck %s --check-prefix=SM110A
+
+; RUN: %if ptxas-sm_101 && ptxas-isa-8.6 %{ llc < %s -mcpu=sm_110 | %ptxas-verify -arch=sm_101 %}
+; RUN: %if ptxas-sm_110 && ptxas-isa-9.0 %{ llc < %s -mcpu=sm_110 -mattr=+ptx90 | %ptxas-verify -arch=sm_110 %}
+
+; SM101: .version 8.6
+; SM101: .target sm_101
+
+; SM101-PTX88: .version 8.8
+; SM101-PTX88: .target sm_101
+
+; SM110: .version 9.0
+; SM110: .target sm_110
+
+; SM101F: .version 8.8
+; SM101F: .target sm_101f
+
+; SM110F: .version 9.0
+; SM110F: .target sm_110f
+
+; SM101A: .version 8.6
+; SM101A: .target sm_101a
+
+; SM110A: .version 9.0
+; SM110A: .target sm_110a
+
+target triple = "nvptx64-nvidia-cuda"
+
+define void @foo() {
+ ret void
+}
diff --git a/llvm/test/CodeGen/NVPTX/sm-version.ll b/llvm/test/CodeGen/NVPTX/sm-version.ll
index 6a8ff3b83fb69..8894b4fe301ef 100644
--- a/llvm/test/CodeGen/NVPTX/sm-version.ll
+++ b/llvm/test/CodeGen/NVPTX/sm-version.ll
@@ -111,9 +111,9 @@
; SM107: .version 9.4
; SM107a: .version 9.4
; SM107f: .version 9.4
-; SM110: .version 9.0
-; SM110a: .version 9.0
-; SM110f: .version 9.0
+; SM110: .version 8.6
+; SM110a: .version 8.6
+; SM110f: .version 8.8
; SM120: .version 8.7
; SM120a: .version 8.7
; SM120f: .version 8.8
@@ -152,9 +152,11 @@
; SM107: .target sm_107
; SM107a: .target sm_107a
; SM107f: .target sm_107f
-; SM110: .target sm_110
-; SM110a: .target sm_110a
-; SM110f: .target sm_110f
+; The sm_11x defaults predate the rename to that name, so they are spelled
+; sm_101x here. See sm-110-rename.ll.
+; SM110: .target sm_101
+; SM110a: .target sm_101a
+; SM110f: .target sm_101f
; SM120: .target sm_120
; SM120a: .target sm_120a
; SM120f: .target sm_120f
More information about the llvm-commits
mailing list