[llvm] [AMDGPU] Make dead SGPR to not depend on exec in `isIgnorableUse` (PR #218942)
Igor Wodiany via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 26 07:46:25 PDT 2026
https://github.com/IgWod created https://github.com/llvm/llvm-project/pull/218942
This creates new sinking opportunities when the SGPR def is dead and as a result can be safely sunk.
Assisted-by: Claude Code
>From 77b5ed7001b8218d5c11d140f2b792a99f826c75 Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Wed, 26 Aug 2026 15:31:33 +0100
Subject: [PATCH] [AMDGPU] Make dead SGPR to not depend on exec
This creates new sinking opportunities when the SGPR def is dead and
as a result can be safely sunk.
Assisted-by: Claude Code
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 +-
llvm/test/CodeGen/AMDGPU/collapse-endcf.ll | 62 ++++++------
.../machine-sink-ignorable-exec-use.mir | 96 +++++++++++++++++++
3 files changed, 127 insertions(+), 35 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index bc419d813f171..6fefced25b171 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -267,10 +267,10 @@ bool SIInstrInfo::resultDependsOnExec(const MachineInstr &MI) const {
if (MI.isConvergent())
return true;
- // If it defines SGPR it depends on EXEC
+ // If it defines an SGPR it depends on EXEC, unless it's dead.
const MachineRegisterInfo &MRI = MI.getMF()->getRegInfo();
for (const MachineOperand &Def : MI.defs()) {
- if (!Def.isReg())
+ if (!Def.isReg() || Def.isDead())
continue;
Register Reg = Def.getReg();
diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
index 181777a6d211d..873d28b54337b 100644
--- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
+++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
@@ -10,29 +10,29 @@ define amdgpu_kernel void @simple_nested_if(ptr addrspace(1) nocapture %arg) {
; GCN-LABEL: simple_nested_if:
; GCN: ; %bb.0: ; %bb
; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 1, v0
-; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GCN-NEXT: s_and_saveexec_b64 s[2:3], vcc
; GCN-NEXT: s_cbranch_execz .LBB0_3
; GCN-NEXT: ; %bb.1: ; %bb.outer.then
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
-; GCN-NEXT: v_lshlrev_b32_e32 v3, 2, v0
-; GCN-NEXT: v_mov_b32_e32 v4, 0
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: s_mov_b32 s2, 0
+; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
+; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; GCN-NEXT: v_mov_b32_e32 v3, 0
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v2, s1
-; GCN-NEXT: v_add_i32_e32 v1, vcc, s0, v3
-; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 2, v0
-; GCN-NEXT: buffer_store_dword v4, v[3:4], s[0:3], 0 addr64
-; GCN-NEXT: s_and_b64 exec, exec, vcc
+; GCN-NEXT: v_add_i32_e32 v1, vcc, s4, v2
+; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 2, v0
+; GCN-NEXT: buffer_store_dword v3, v[2:3], s[4:7], 0 addr64
+; GCN-NEXT: s_and_b64 exec, exec, s[0:1]
; GCN-NEXT: s_cbranch_execz .LBB0_3
; GCN-NEXT: ; %bb.2: ; %bb.inner.then
-; GCN-NEXT: s_mov_b32 s0, s2
-; GCN-NEXT: s_mov_b32 s1, s2
+; GCN-NEXT: v_mov_b32_e32 v0, s5
+; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v0, vcc
+; GCN-NEXT: s_mov_b32 s4, s6
+; GCN-NEXT: s_mov_b32 s5, s6
; GCN-NEXT: v_mov_b32_e32 v0, 1
-; GCN-NEXT: buffer_store_dword v0, v[1:2], s[0:3], 0 addr64 offset:4
+; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr64 offset:4
; GCN-NEXT: .LBB0_3: ; %bb.outer.end
-; GCN-NEXT: s_or_b64 exec, exec, s[6:7]
+; GCN-NEXT: s_or_b64 exec, exec, s[2:3]
; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, 3
; GCN-NEXT: v_mov_b32_e32 v1, 0
@@ -371,45 +371,41 @@ bb.outer.end: ; preds = %bb.inner.then, %bb
define amdgpu_kernel void @nested_if_if_else(ptr addrspace(1) nocapture %arg) {
; GCN-LABEL: nested_if_if_else:
; GCN: ; %bb.0: ; %bb
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
+; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; GCN-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GCN-NEXT: v_mov_b32_e32 v2, 0
-; GCN-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NEXT: s_mov_b32 s2, 0
+; GCN-NEXT: s_mov_b32 s7, 0xf000
+; GCN-NEXT: s_mov_b32 s6, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v4, s1
-; GCN-NEXT: v_add_i32_e32 v3, vcc, s0, v1
-; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
-; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 1, v0
-; GCN-NEXT: buffer_store_dword v2, v[1:2], s[0:3], 0 addr64
-; GCN-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GCN-NEXT: v_add_i32_e32 v3, vcc, s4, v1
+; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 1, v0
+; GCN-NEXT: buffer_store_dword v2, v[1:2], s[4:7], 0 addr64
+; GCN-NEXT: s_and_saveexec_b64 s[2:3], s[0:1]
; GCN-NEXT: s_cbranch_execz .LBB2_5
; GCN-NEXT: ; %bb.1: ; %bb.outer.then
+; GCN-NEXT: v_mov_b32_e32 v1, s5
+; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 2, v0
-; GCN-NEXT: s_and_saveexec_b64 s[2:3], vcc
-; GCN-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
+; GCN-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GCN-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
; GCN-NEXT: s_cbranch_execz .LBB2_3
; GCN-NEXT: ; %bb.2: ; %bb.else
-; GCN-NEXT: s_mov_b32 s6, 0
-; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s6
; GCN-NEXT: v_mov_b32_e32 v0, 2
; GCN-NEXT: buffer_store_dword v0, v[3:4], s[4:7], 0 addr64 offset:8
; GCN-NEXT: ; implicit-def: $vgpr3_vgpr4
; GCN-NEXT: .LBB2_3: ; %Flow
-; GCN-NEXT: s_andn2_saveexec_b64 s[2:3], s[2:3]
+; GCN-NEXT: s_andn2_saveexec_b64 s[0:1], s[0:1]
; GCN-NEXT: s_cbranch_execz .LBB2_5
; GCN-NEXT: ; %bb.4: ; %bb.then
-; GCN-NEXT: s_mov_b32 s6, 0
-; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s4, s6
; GCN-NEXT: s_mov_b32 s5, s6
; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, 1
; GCN-NEXT: buffer_store_dword v0, v[3:4], s[4:7], 0 addr64 offset:4
; GCN-NEXT: .LBB2_5: ; %bb.outer.end
-; GCN-NEXT: s_or_b64 exec, exec, s[0:1]
+; GCN-NEXT: s_or_b64 exec, exec, s[2:3]
; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, 3
; GCN-NEXT: s_mov_b32 m0, -1
diff --git a/llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir b/llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
index cdc111313b509..b1bcd89e06c28 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
+++ b/llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
@@ -800,3 +800,99 @@ body: |
bb.3:
S_ENDPGM 0, implicit %13
...
+---
+name: test_sink_add_co_dead_carry_out
+tracksRegLiveness: true
+machineFunctionInfo:
+ isEntryFunction: true
+body: |
+ ; GFX9-LABEL: name: test_sink_add_co_dead_carry_out
+ ; GFX9: bb.0:
+ ; GFX9-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; GFX9-NEXT: liveins: $vgpr0
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX9-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I32_e64 [[COPY]], 1, implicit $exec
+ ; GFX9-NEXT: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF [[V_CMP_LT_I32_e64_]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ ; GFX9-NEXT: S_BRANCH %bb.1
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: bb.1:
+ ; GFX9-NEXT: successors: %bb.2(0x80000000)
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[COPY]], 0, implicit $exec
+ ; GFX9-NEXT: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[V_ADD_CO_U32_e64_]], [[V_ADD_CO_U32_e64_]], implicit $exec
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: bb.2:
+ ; GFX9-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[V_MOV_B32_e32_]], %bb.0, [[V_MAX_I32_e64_]], %bb.1
+ ; GFX9-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ ; GFX9-NEXT: S_ENDPGM 0, implicit [[PHI]]
+ bb.0:
+ successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ liveins: $vgpr0
+
+ %0:vgpr_32 = COPY $vgpr0
+ %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ %2:vgpr_32, dead %3:sreg_64_xexec = V_ADD_CO_U32_e64 %0, %0, 0, implicit $exec
+ %4:sreg_64 = V_CMP_LT_I32_e64 %0, 1, implicit $exec
+ %5:sreg_64 = SI_IF %4, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ %6:vgpr_32 = V_MAX_I32_e64 %2, %2, implicit $exec
+
+ bb.2:
+ %7:vgpr_32 = PHI %1, %bb.0, %6, %bb.1
+ SI_END_CF %5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ S_ENDPGM 0, implicit %7
+...
+---
+name: test_no_sink_add_co_live_carry_out
+tracksRegLiveness: true
+machineFunctionInfo:
+ isEntryFunction: true
+body: |
+ ; GFX9-LABEL: name: test_no_sink_add_co_live_carry_out
+ ; GFX9: bb.0:
+ ; GFX9-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; GFX9-NEXT: liveins: $vgpr0
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+ ; GFX9-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ ; GFX9-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[COPY]], 0, implicit $exec
+ ; GFX9-NEXT: [[V_CMP_LT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_I32_e64 [[COPY]], 1, implicit $exec
+ ; GFX9-NEXT: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF [[V_CMP_LT_I32_e64_]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ ; GFX9-NEXT: S_BRANCH %bb.1
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: bb.1:
+ ; GFX9-NEXT: successors: %bb.2(0x80000000)
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, [[V_ADD_CO_U32_e64_]], [[V_ADD_CO_U32_e64_1]], implicit $exec
+ ; GFX9-NEXT: {{ $}}
+ ; GFX9-NEXT: bb.2:
+ ; GFX9-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[V_MOV_B32_e32_]], %bb.0, [[V_CNDMASK_B32_e64_]], %bb.1
+ ; GFX9-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ ; GFX9-NEXT: S_ENDPGM 0, implicit [[PHI]]
+ bb.0:
+ successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ liveins: $vgpr0
+
+ %0:vgpr_32 = COPY $vgpr0
+ %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+ %2:vgpr_32, %3:sreg_64_xexec = V_ADD_CO_U32_e64 %0, %0, 0, implicit $exec
+ %4:sreg_64 = V_CMP_LT_I32_e64 %0, 1, implicit $exec
+ %5:sreg_64 = SI_IF %4, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.2(0x80000000)
+
+ %6:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, %2, %3, implicit $exec
+
+ bb.2:
+ %7:vgpr_32 = PHI %1, %bb.0, %6, %bb.1
+ SI_END_CF %5, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ S_ENDPGM 0, implicit %7
+...
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