[llvm] [AMDGPU] merge 16bit mov pairs in post-RA peephole (PR #208625)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/lib/Target/AMDGPU/SIPostRA16BitMovFolding.cpp llvm/lib/Target/AMDGPU/AMDGPU.h llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp --diff_from_common_commit
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIPostRA16BitMovFolding.cpp b/llvm/lib/Target/AMDGPU/SIPostRA16BitMovFolding.cpp
index abe0ccdf2..c2e57bcf9 100644
--- a/llvm/lib/Target/AMDGPU/SIPostRA16BitMovFolding.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPostRA16BitMovFolding.cpp
@@ -40,11 +40,12 @@ private:
   bool mergeSingleMovB16Pair(MachineInstr &Lo, MachineInstr &Hi,
                              bool IsHiFirst) const;
   bool mergeMovB16Pairs(MachineFunction &MF) const;
+
 public:
   bool run(MachineFunction &MF);
 };
 
-class SIPostRA16BitMovFoldingLegacy: public MachineFunctionPass {
+class SIPostRA16BitMovFoldingLegacy : public MachineFunctionPass {
 public:
   static char ID;
 
@@ -55,7 +56,7 @@ public:
   }
 
   void getAnalysisUsage(AnalysisUsage &AU) const override {
-	AU.setPreservesAll();
+    AU.setPreservesAll();
     MachineFunctionPass::getAnalysisUsage(AU);
   }
 
@@ -76,11 +77,10 @@ char &llvm::SIPostRA16BitMovFoldingLegacyID = SIPostRA16BitMovFoldingLegacy::ID;
 // Helper: extract the src operand and whether it is from the hi16 half.
 // Post-RA, both V_MOV_B16_t16_e32 and V_MOV_B16_t16_e64 use VGPR_16 dst
 // physical registers whose encoding already encodes hi/lo (IS_HI16 bit).
-void SIPostRA16BitMovFolding::getMovB16Info(const MachineInstr &MI,
-                                      const SIRegisterInfo *TRI,
-                                      MCRegister &SrcReg16, bool &SrcIsVGPR,
-                                      MCRegister &SrcReg32, bool &SrcIsHi,
-                                      bool &SrcIsImm, int64_t &ImmVal) const {
+void SIPostRA16BitMovFolding::getMovB16Info(
+    const MachineInstr &MI, const SIRegisterInfo *TRI, MCRegister &SrcReg16,
+    bool &SrcIsVGPR, MCRegister &SrcReg32, bool &SrcIsHi, bool &SrcIsImm,
+    int64_t &ImmVal) const {
   SrcIsImm = false;
   SrcIsHi = false;
   SrcIsVGPR = false;
@@ -120,8 +120,8 @@ void SIPostRA16BitMovFolding::getMovB16Info(const MachineInstr &MI,
 //   v_mov_b16 v0.l, v.x/s    v_mov_b16 v0.h, v.y/s    => v_perm_b32_e64 v0, v.x/s, v.y/s, mask
 // clang-format on
 bool SIPostRA16BitMovFolding::mergeSingleMovB16Pair(MachineInstr &Lo,
-                                              MachineInstr &Hi,
-                                              bool IsHiFirst) const {
+                                                    MachineInstr &Hi,
+                                                    bool IsHiFirst) const {
   // Lo and Hi share the same Dst32
   MCRegister LoDst = Lo.getOperand(0).getReg().asMCReg();
   MCRegister HiDst = Hi.getOperand(0).getReg().asMCReg();
@@ -190,9 +190,9 @@ bool SIPostRA16BitMovFolding::mergeSingleMovB16Pair(MachineInstr &Lo,
   // Pattern: v_mov_b16 v0.l, v2.x/s2 + v_mov_b16 v0.h, v3.y/s3
   //   => v_perm_b32_e64  v0,v3.y/s3,v2.x/s2, mask
   if (!HiSrcIsImm && !LoSrcIsImm) {
-	// Violate constant bus restriction
-	if (!LoSrcIsVGPR && !HiSrcIsVGPR && HiSrc32 != LoSrc32)
-		return false;
+    // Violate constant bus restriction
+    if (!LoSrcIsVGPR && !HiSrcIsVGPR && HiSrc32 != LoSrc32)
+      return false;
     unsigned MaskHiSrc = HiSrcIsHi ? 0x0706 : 0x0504;
     unsigned MaskLoSrc = LoSrcIsHi ? 0x0302 : 0x0100;
     BuildMI(MBB, Selected, DL, TII->get(AMDGPU::V_PERM_B32_e64), Dst32)
@@ -306,7 +306,7 @@ bool SIPostRA16BitMovFolding::mergeMovB16Pairs(MachineFunction &MF) const {
         continue;
       }
 
-	  LLVM_DEBUG(dbgs() << "Checking MI:" << MI << "\n");
+      LLVM_DEBUG(dbgs() << "Checking MI:" << MI << "\n");
       MCRegister DstReg = MI.getOperand(0).getReg().asMCReg();
       bool DstIsHi = AMDGPU::isHi16Reg(DstReg, *TRI);
       MCRegister Dst32 = TRI->get32BitRegister(DstReg);
@@ -346,7 +346,7 @@ llvm::SIPostRA16BitMovFoldingPass::run(MachineFunction &MF,
 }
 
 bool SIPostRA16BitMovFolding::run(MachineFunction &MF) {
-  const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
+  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
   TII = ST.getInstrInfo();
   bool Changed = false;

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https://github.com/llvm/llvm-project/pull/208625