[llvm] [WebAssembly] Expand v8f16 SELECT_CC (PR #218922)

[Anutosh Bhat via llvm-commits]

https://github.com/anutosh491 updated https://github.com/llvm/llvm-project/pull/218922

>From 8db08699549c9e690c791ada921d4413dd532d14 Mon Sep 17 00:00:00 2001
From: anutosh491 <andersonbhat491 at gmail.com>
Date: Wed, 26 Aug 2026 19:07:47 +0530
Subject: [PATCH 1/2] [WebAssembly] Expand v8f16 SELECT_CC

---
 .../WebAssembly/WebAssemblyISelLowering.cpp   |  3 +-
 .../CodeGen/WebAssembly/f16-intrinsics.ll     | 32 +++++++++++++++++++
 2 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index bd8c9169eabba..104960e6a77a3 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -391,7 +391,8 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
 
   // There is no vector conditional select instruction
   for (auto T :
-       {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64, MVT::v2f64})
+       {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
+        MVT::v2f64, MVT::v8f16})
     setOperationAction(ISD::SELECT_CC, T, Expand);
 
   // We have custom switch handling.
diff --git a/llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll b/llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
index 26722f137fa06..4761685f651f6 100644
--- a/llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
+++ b/llvm/test/CodeGen/WebAssembly/f16-intrinsics.ll
@@ -122,6 +122,38 @@ define <8 x half> @vselect_cmp_v8f16(<8 x half> %a, <8 x half> %b,
   ret <8 x half> %result
 }
 
+; CHECK-LABEL: select_cmp_v8f16:
+; CHECK:       i32.const $push0=, 0
+; CHECK-NEXT:  i32.lt_s $push1=, $0, $pop0
+; CHECK-NEXT:  v128.select $push2=, $1, $2, $pop1
+; CHECK-NEXT:  return $pop2
+define <8 x half> @select_cmp_v8f16(i32 %i, <8 x half> %x,
+                                     <8 x half> %y) {
+  %cond = icmp slt i32 %i, 0
+  %result = select i1 %cond, <8 x half> %x, <8 x half> %y
+  ret <8 x half> %result
+}
+
+; CHECK-LABEL: select_ne_v8f16:
+; CHECK:       v128.select $push0=, $1, $2, $0
+; CHECK-NEXT:  return $pop0
+define <8 x half> @select_ne_v8f16(i32 %i, <8 x half> %x,
+                                    <8 x half> %y) {
+  %cond = icmp ne i32 %i, 0
+  %result = select i1 %cond, <8 x half> %x, <8 x half> %y
+  ret <8 x half> %result
+}
+
+; CHECK-LABEL: select_eq_v8f16:
+; CHECK:       v128.select $push0=, $2, $1, $0
+; CHECK-NEXT:  return $pop0
+define <8 x half> @select_eq_v8f16(i32 %i, <8 x half> %x,
+                                    <8 x half> %y) {
+  %cond = icmp eq i32 %i, 0
+  %result = select i1 %cond, <8 x half> %x, <8 x half> %y
+  ret <8 x half> %result
+}
+
 ; CHECK-LABEL: add_v8f16:
 ; CHECK:       f16x8.add $push0=, $0, $1
 ; CHECK-NEXT:  return $pop0

>From 324975e35cd65490f02fa17b53c3f8fc746c7db8 Mon Sep 17 00:00:00 2001
From: Anutosh Bhat <andersonbhat491 at gmail.com>
Date: Wed, 26 Aug 2026 19:33:23 +0530
Subject: [PATCH 2/2] code format

---
 llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
index 104960e6a77a3..cbe95318186bb 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
@@ -390,9 +390,8 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
         setOperationAction(Op, T, Expand);
 
   // There is no vector conditional select instruction
-  for (auto T :
-       {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
-        MVT::v2f64, MVT::v8f16})
+  for (auto T : {MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v4f32, MVT::v2i64,
+                 MVT::v2f64, MVT::v8f16})
     setOperationAction(ISD::SELECT_CC, T, Expand);
 
   // We have custom switch handling.