[llvm] [AMDGPU] Model ordered XDL writes in expert scheduling (PR #218326)

[Jay Foad via llvm-commits]

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@@ -1018,6 +1018,10 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
 
   bool isXDL(const MachineInstr &MI) const;
 
+  /// On gfx1250, XDL VA_VDST decrements are ordered after earlier decrements
+  /// when the destination spans at least eight sequential VGPRs.
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jayfoad wrote:

Does this mean that such XDL instructions are ordered vs other such XDL instructions, or ordered vs all prior VALU instructions of any type?

https://github.com/llvm/llvm-project/pull/218326