[llvm] [GlobalISel] Preserve destination type kind when lowering G_EXTRACT (PR #218345)
Keshav Vinayak Jha via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 26 04:47:42 PDT 2026
https://github.com/keshavvinayak01 updated https://github.com/llvm/llvm-project/pull/218345
>From dbd41d3235983fbf8e0c8c94f836c9ef4a3348de Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Mon, 24 Aug 2026 13:51:20 +0530
Subject: [PATCH 1/3] [GlobalISel] Preserve specific LLTs in constrainRegAttrs
Do not replace a specific extended LLT with a compatible any-scalar type when constraining register attributes. Continue refining an any-scalar type to a more specific constraining type, and cover both argument orders.
Co-authored-by: GPT-5 <noreply at openai.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
llvm/lib/CodeGen/MachineRegisterInfo.cpp | 5 +++-
.../CodeGen/GlobalISel/CMakeLists.txt | 1 +
.../GlobalISel/MachineRegisterInfoTest.cpp | 27 +++++++++++++++++++
3 files changed, 32 insertions(+), 1 deletion(-)
create mode 100644 llvm/unittests/CodeGen/GlobalISel/MachineRegisterInfoTest.cpp
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index dbba413548018..fb7430195aef6 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -111,7 +111,10 @@ MachineRegisterInfo::constrainRegAttrs(Register Reg,
} else if (RegCB != ConstrainingRegCB)
return false;
}
- if (ConstrainingRegTy.isValid())
+ // Refine an any-scalar element type to the constraining type, but do not
+ // discard a more specific extended LLT in favor of an any-scalar type.
+ if (ConstrainingRegTy.isValid() &&
+ (!RegTy.isValid() || RegTy.getScalarType().isAnyScalar()))
setType(Reg, ConstrainingRegTy);
return true;
}
diff --git a/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt b/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
index e85a3aa72c961..a16d70bf6d973 100644
--- a/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
+++ b/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
@@ -22,6 +22,7 @@ add_llvm_unittest(GlobalISelTests
LegalizerHelperTest.cpp
LegalizerInfoTest.cpp
MachineIRBuilderTest.cpp
+ MachineRegisterInfoTest.cpp
GISelMITest.cpp
PatternMatchTest.cpp
KnownBitsTest.cpp
diff --git a/llvm/unittests/CodeGen/GlobalISel/MachineRegisterInfoTest.cpp b/llvm/unittests/CodeGen/GlobalISel/MachineRegisterInfoTest.cpp
new file mode 100644
index 0000000000000..1af169c43d83d
--- /dev/null
+++ b/llvm/unittests/CodeGen/GlobalISel/MachineRegisterInfoTest.cpp
@@ -0,0 +1,27 @@
+//===- MachineRegisterInfoTest.cpp ---------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "GISelMITest.h"
+
+TEST_F(AMDGPUGISelMITest, ConstrainRegAttrsPreservesSpecificLLT) {
+ setUp();
+ if (!TM)
+ GTEST_SKIP();
+
+ const LLT S64 = LLT::scalar(64);
+ const LLT I64 = LLT::integer(64);
+ Register SpecificReg = MRI->createGenericVirtualRegister(I64);
+ Register AnyReg = MRI->createGenericVirtualRegister(S64);
+
+ EXPECT_TRUE(MRI->constrainRegAttrs(SpecificReg, AnyReg));
+ EXPECT_TRUE(MRI->getType(SpecificReg).isInteger());
+
+ EXPECT_TRUE(MRI->constrainRegAttrs(AnyReg, SpecificReg));
+ EXPECT_TRUE(MRI->getType(AnyReg).isInteger());
+}
>From 6ab0f47cb644d1b95b1380123016096b14c67fda Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Wed, 26 Aug 2026 11:27:54 +0530
Subject: [PATCH 2/3] [GlobalISel] Preserve destination type kind in extract
lowering
Use an integer source cast when lowering G_EXTRACT to a specific result while retaining any-scalar casts for any-scalar results. This avoids generating mixed s64 and i64 MIR in AMDGPU address-space casts.
Drop the broader constrainRegAttrs behavior change and update the affected AMDGPU legalization checks.
Co-authored-by: GPT-5 <noreply at openai.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 3 ++-
llvm/lib/CodeGen/MachineRegisterInfo.cpp | 5 +---
.../CodeGen/AMDGPU/GlobalISel/global-value.ll | 8 +++---
.../GlobalISel/legalize-addrspacecast.mir | 24 ++++++++---------
.../AMDGPU/GlobalISel/legalize-extract.mir | 4 +--
.../CodeGen/GlobalISel/CMakeLists.txt | 1 -
.../GlobalISel/MachineRegisterInfoTest.cpp | 27 -------------------
7 files changed, 21 insertions(+), 51 deletions(-)
delete mode 100644 llvm/unittests/CodeGen/GlobalISel/MachineRegisterInfoTest.cpp
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 6f85390fd4ede..0fe2c9662f87d 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -9907,7 +9907,8 @@ LegalizerHelper::lowerExtract(MachineInstr &MI) {
(SrcTy.isVector() && DstTy == SrcTy.getElementType()))) {
LLT SrcIntTy = SrcTy;
if (!SrcTy.isScalar()) {
- SrcIntTy = LLT::scalar(SrcTy.getSizeInBits());
+ SrcIntTy = DstTy.isAnyScalar() ? LLT::scalar(SrcTy.getSizeInBits())
+ : LLT::integer(SrcTy.getSizeInBits());
SrcReg = MIRBuilder.buildCast(SrcIntTy, SrcReg).getReg(0);
}
diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
index fb7430195aef6..dbba413548018 100644
--- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp
+++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp
@@ -111,10 +111,7 @@ MachineRegisterInfo::constrainRegAttrs(Register Reg,
} else if (RegCB != ConstrainingRegCB)
return false;
}
- // Refine an any-scalar element type to the constraining type, but do not
- // discard a more specific extended LLT in favor of an any-scalar type.
- if (ConstrainingRegTy.isValid() &&
- (!RegTy.isValid() || RegTy.getScalarType().isAnyScalar()))
+ if (ConstrainingRegTy.isValid())
setType(Reg, ConstrainingRegTy);
return true;
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
index ee34c43485da0..5f38d23b7528c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-value.ll
@@ -142,8 +142,8 @@ define ptr addrspace(6) @external_constant32_got() {
; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @external_constant32, target-flags(amdgpu-gotprel32-hi) @external_constant32, implicit-def $scc
; GCN-NEXT: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[SI_PC_ADD_REL_OFFSET]](p4) :: (dereferenceable invariant load (p4) from got, addrspace 4)
- ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[LOAD]](p4)
- ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[LOAD]](p4)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](i32)
; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
; GCN-NEXT: SI_RETURN implicit $vgpr0
@@ -161,8 +161,8 @@ define ptr addrspace(6) @internal_constant32_pcrel() {
; GCN-LABEL: name: internal_constant32_pcrel
; GCN: bb.1 (%ir-block.0):
; GCN-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64(p4) = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @internal_constant32, target-flags(amdgpu-rel32-hi) @internal_constant32, implicit-def $scc
- ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[SI_PC_ADD_REL_OFFSET]](p4)
- ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[SI_PC_ADD_REL_OFFSET]](p4)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](i32)
; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
; GCN-NEXT: SI_RETURN implicit $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
index f6fcff54d2e8a..16b272e19c16a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
@@ -186,8 +186,8 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GCN-NEXT: [[C:%[0-9]+]]:_(p5) = G_CONSTANT i32 -1
; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY]](p0)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p5) = G_INTTOPTR [[TRUNC]](i32)
; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[C1]]
; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p5) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]]
@@ -257,8 +257,8 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; GCN-NEXT: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY]](p0)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](i32)
; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](p0), [[C1]]
; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]]
@@ -330,13 +330,13 @@ body: |
; GCN-NEXT: [[UV:%[0-9]+]]:_(p0), [[UV1:%[0-9]+]]:_(p0) = G_UNMERGE_VALUES [[COPY]](<2 x p0>)
; GCN-NEXT: [[C:%[0-9]+]]:_(p3) = G_CONSTANT i32 -1
; GCN-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
- ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[UV]](p0)
- ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[UV]](p0)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](i32)
; GCN-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV]](p0), [[C1]]
; GCN-NEXT: [[SELECT:%[0-9]+]]:_(p3) = G_SELECT [[ICMP]](s1), [[INTTOPTR]], [[C]]
- ; GCN-NEXT: [[PTRTOINT1:%[0-9]+]]:_(s64) = G_PTRTOINT [[UV1]](p0)
- ; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT1]](s64)
+ ; GCN-NEXT: [[PTRTOINT1:%[0-9]+]]:_(i64) = G_PTRTOINT [[UV1]](p0)
+ ; GCN-NEXT: [[TRUNC1:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT1]](i64)
; GCN-NEXT: [[INTTOPTR1:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC1]](i32)
; GCN-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[UV1]](p0), [[C1]]
; GCN-NEXT: [[SELECT1:%[0-9]+]]:_(p3) = G_SELECT [[ICMP1]](s1), [[INTTOPTR1]], [[C]]
@@ -418,8 +418,8 @@ body: |
; GCN: liveins: $vgpr0_vgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(p4) = COPY $vgpr0_vgpr1
- ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p4)
- ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY]](p4)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](i32)
; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
%0:_(p4) = COPY $vgpr0_vgpr1
@@ -477,8 +477,8 @@ body: |
; GCN: liveins: $vgpr0_vgpr1
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
+ ; GCN-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY]](p0)
+ ; GCN-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
; GCN-NEXT: [[INTTOPTR:%[0-9]+]]:_(p6) = G_INTTOPTR [[TRUNC]](i32)
; GCN-NEXT: $vgpr0 = COPY [[INTTOPTR]](p6)
%0:_(p0) = COPY $vgpr0_vgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
index ef6699139ca7d..d7bd5cb16eebf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
@@ -1428,8 +1428,8 @@ body: |
; CHECK: liveins: $vgpr0_vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](s64)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i64) = G_PTRTOINT [[COPY]](p0)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(i32) = G_TRUNC [[PTRTOINT]](i64)
; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p3) = G_INTTOPTR [[TRUNC]](i32)
; CHECK-NEXT: $vgpr0 = COPY [[INTTOPTR]](p3)
%0:_(p0) = COPY $vgpr0_vgpr1
diff --git a/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt b/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
index a16d70bf6d973..e85a3aa72c961 100644
--- a/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
+++ b/llvm/unittests/CodeGen/GlobalISel/CMakeLists.txt
@@ -22,7 +22,6 @@ add_llvm_unittest(GlobalISelTests
LegalizerHelperTest.cpp
LegalizerInfoTest.cpp
MachineIRBuilderTest.cpp
- MachineRegisterInfoTest.cpp
GISelMITest.cpp
PatternMatchTest.cpp
KnownBitsTest.cpp
diff --git a/llvm/unittests/CodeGen/GlobalISel/MachineRegisterInfoTest.cpp b/llvm/unittests/CodeGen/GlobalISel/MachineRegisterInfoTest.cpp
deleted file mode 100644
index 1af169c43d83d..0000000000000
--- a/llvm/unittests/CodeGen/GlobalISel/MachineRegisterInfoTest.cpp
+++ /dev/null
@@ -1,27 +0,0 @@
-//===- MachineRegisterInfoTest.cpp ---------------------------------------===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "GISelMITest.h"
-
-TEST_F(AMDGPUGISelMITest, ConstrainRegAttrsPreservesSpecificLLT) {
- setUp();
- if (!TM)
- GTEST_SKIP();
-
- const LLT S64 = LLT::scalar(64);
- const LLT I64 = LLT::integer(64);
- Register SpecificReg = MRI->createGenericVirtualRegister(I64);
- Register AnyReg = MRI->createGenericVirtualRegister(S64);
-
- EXPECT_TRUE(MRI->constrainRegAttrs(SpecificReg, AnyReg));
- EXPECT_TRUE(MRI->getType(SpecificReg).isInteger());
-
- EXPECT_TRUE(MRI->constrainRegAttrs(AnyReg, SpecificReg));
- EXPECT_TRUE(MRI->getType(AnyReg).isInteger());
-}
>From b305ffe99122eb341b180c7048ca72ef8b6e8cb0 Mon Sep 17 00:00:00 2001
From: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
Date: Wed, 26 Aug 2026 17:17:23 +0530
Subject: [PATCH 3/3] [GlobalISel] Use integer LLTs for non-scalar extracts
Use integer intermediates when lowering extracts from pointer or vector sources, since the generated cast, shift, and truncation are integer operations.
Co-authored-by: GPT-5 <noreply at openai.com>
Signed-off-by: Keshav Vinayak Jha <keshavvinayakjha at gmail.com>
---
.../CodeGen/GlobalISel/LegalizerHelper.cpp | 3 +-
.../AMDGPU/GlobalISel/legalize-extract.mir | 28 +++++++++----------
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 0fe2c9662f87d..a63bd3e5fee1a 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -9907,8 +9907,7 @@ LegalizerHelper::lowerExtract(MachineInstr &MI) {
(SrcTy.isVector() && DstTy == SrcTy.getElementType()))) {
LLT SrcIntTy = SrcTy;
if (!SrcTy.isScalar()) {
- SrcIntTy = DstTy.isAnyScalar() ? LLT::scalar(SrcTy.getSizeInBits())
- : LLT::integer(SrcTy.getSizeInBits());
+ SrcIntTy = LLT::integer(SrcTy.getSizeInBits());
SrcReg = MIRBuilder.buildCast(SrcIntTy, SrcReg).getReg(0);
}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
index d7bd5cb16eebf..e5bd33ebed213 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract.mir
@@ -1006,10 +1006,10 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](i32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 1
%2:_(s32) = G_ANYEXT %1
@@ -1026,10 +1026,10 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY]](<2 x s16>)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 8
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](i32)
%0:_(<2 x s16>) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 8
%2:_(s32) = G_ANYEXT %1
@@ -1140,8 +1140,8 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
- ; CHECK-NEXT: $vgpr0 = COPY [[PTRTOINT]](s32)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY]](p3)
+ ; CHECK-NEXT: $vgpr0 = COPY [[PTRTOINT]](i32)
%0:_(p3) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 0
%2:_(s32) = G_ANYEXT %1
@@ -1158,10 +1158,10 @@ body: |
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
- ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY]](p3)
- ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[PTRTOINT]], [[C]](s32)
- ; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](s32)
+ ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(i32) = G_PTRTOINT [[COPY]](p3)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[PTRTOINT]], [[C]](i32)
+ ; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](i32)
%0:_(p3) = COPY $vgpr0
%1:_(s16) = G_EXTRACT %0, 1
%2:_(s32) = G_ANYEXT %1
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