[llvm] [AMDGPU] Regenerate CHECK lines for sdwa-peephole-movrels.mir (NFC) (PR #218888)

[Arseniy Obolenskiy via llvm-commits]

https://github.com/aobolensk created https://github.com/llvm/llvm-project/pull/218888

Address post-merge comment from https://github.com/llvm/llvm-project/pull/218592

>From efa1078422b91bdd66f4860645adec9557a50024 Mon Sep 17 00:00:00 2001
From: Arseniy Obolenskiy <arseniy.obolenskiy at amd.com>
Date: Wed, 26 Aug 2026 13:10:06 +0200
Subject: [PATCH] [AMDGPU] Regenerate CHECK lines for sdwa-peephole-movrels.mir
 (NFC)

Address post-merge comment from https://github.com/llvm/llvm-project/pull/218592
---
 .../CodeGen/AMDGPU/sdwa-peephole-movrels.mir    | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/sdwa-peephole-movrels.mir b/llvm/test/CodeGen/AMDGPU/sdwa-peephole-movrels.mir
index 20702fcf92b4b..6af794d7f7ce8 100644
--- a/llvm/test/CodeGen/AMDGPU/sdwa-peephole-movrels.mir
+++ b/llvm/test/CodeGen/AMDGPU/sdwa-peephole-movrels.mir
@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
 # RUN: llc -mtriple=amdgpu8.03 -run-pass=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck %s
 # RUN: llc -mtriple=amdgpu9 -run-pass=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck %s
 # RUN: llc -mtriple=amdgpu10.10 -run-pass=si-peephole-sdwa -verify-machineinstrs -o - %s | FileCheck %s
@@ -13,8 +14,13 @@ body: |
     liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $sgpr0
 
     ; CHECK-LABEL: name: movrels_dst_no_sdwa
-    ; CHECK: V_MOVRELS_B32_e32
-    ; CHECK-NOT: V_MOVRELS_B32_sdwa
+    ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, $sgpr0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
+    ; CHECK-NEXT: $m0 = COPY $sgpr0
+    ; CHECK-NEXT: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
+    ; CHECK-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 16, [[V_MOVRELS_B32_e32_]], implicit $exec
+    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_LSHLREV_B32_e64_]]
     %0:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
     $m0 = COPY $sgpr0
     %1:vgpr_32 = V_MOVRELS_B32_e32 %0.sub0, implicit $m0, implicit $exec, implicit %0
@@ -31,7 +37,12 @@ body: |
     liveins: $vgpr0, $vgpr1
 
     ; CHECK-LABEL: name: or_dst_sdwa
-    ; CHECK: V_OR_B32_sdwa
+    ; CHECK: liveins: $vgpr0, $vgpr1
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; CHECK-NEXT: [[V_OR_B32_sdwa:%[0-9]+]]:vgpr_32 = V_OR_B32_sdwa 0, [[COPY]], 0, [[COPY1]], 0, 5, 0, 6, 6, implicit $exec
+    ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_OR_B32_sdwa]]
     %0:vgpr_32 = COPY $vgpr0
     %1:vgpr_32 = COPY $vgpr1
     %2:vgpr_32 = V_OR_B32_e64 %0, %1, implicit $exec