[llvm] [RISCV][MC] Prioritize features in MultiMismatchFallback (PR #215737)

[via llvm-commits]

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@@ -1866,6 +1866,15 @@ class AsmParser {
   // messages.
   bit ReportMultipleNearMisses = false;
 
+  // PrioritizeFeatureInMultiMismatchFallback -
+  // When 0, retain the first operand near-miss as the fallback diagnostic when an
+  // instruction has multiple invalid operands.
+  // When 1, prioritize a feature near-miss over the first operand near-miss when
+  // recording a MultiMismatchFallback entry, so that diagnostics point to the
+  // missing extension rather than an operand mismatch.
+  // Only effective when ReportMultipleNearMisses is also 1.
+  bit PrioritizeFeatureInMultiMismatchFallback = false;
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saloni-shinde-Q wrote:

I found that approximately 15 ARM test files require expected-diagnostic updates.

One affected case is `msr basepri, r0` with `-triple=thumbv6`, which currently reports `requires arm-mode`. However, the same instruction is accepted for an M-profile Thumb target, for example with `-triple=thumbv7m-apple-darwin`.

Internally, `Feature_IsARMBit` is printed as `arm-mode`, and `IsARM` is only set when `ModeThumb` is false. For `thumbv6`, the relevant state is roughly:
  ModeThumb = true
  IsARM = false
  IsMClass = false

The matcher has an ARM opcode variant with:
  { ARM::MSR, ..., AMFBS_IsARM, ... }

Since `IsARM` is false, that opcode variant failed its feature check and it reports `requires arm-mode`. I think that diagnostic is misleading here. For an M-profile Thumb target like `thumbv7m`, the relevant opcode variant is `t2MSR_M` with `AMFBS_IsThumb_IsMClass`, so the instruction is accepted.

https://github.com/llvm/llvm-project/pull/215737