[llvm] [AArch64][RegAlloc] Enable callee-saved register optimization for AArch64 (PR #214773)
Shreeyash Pandey via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 26 00:24:15 PDT 2026
https://github.com/bojle updated https://github.com/llvm/llvm-project/pull/214773
>From 96c5513c7764afb20e1b77b5a0e6cc275615fb3c Mon Sep 17 00:00:00 2001
From: Shreeyash Pandey <shrpand at qti.qualcomm.com>
Date: Wed, 5 Aug 2026 08:53:04 +0000
Subject: [PATCH 1/3] Enable new cost
Signed-off-by: Shreeyash Pandey <shrpand at qti.qualcomm.com>
---
llvm/lib/CodeGen/RegAllocGreedy.cpp | 2 +-
llvm/lib/Target/AArch64/AArch64RegisterInfo.h | 10 ++++------
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index d534a71a38d0d..702088823417f 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -118,7 +118,7 @@ CSRFirstTimeCost("regalloc-csr-first-time-cost",
static cl::opt<unsigned> CSRCostScale(
"regalloc-csr-cost-scale",
cl::desc("Scale for the callee-saved register cost, in percentage."),
- cl::init(80), cl::Hidden);
+ cl::init(90), cl::Hidden);
static cl::opt<unsigned long> GrowRegionComplexityBudget(
"grow-region-complexity-budget",
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
index 681ede4584a3b..7fdbf1b04439c 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
@@ -54,17 +54,15 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
const uint32_t *getDarwinCallPreservedMask(const MachineFunction &MF,
CallingConv::ID) const;
- unsigned getCSRCost() const override {
- // The cost will be compared against BlockFrequency where entry has the
- // value of 1 << 14. A value of 5 will choose to spill or split really
- // cold path instead of using a callee-saved register.
- return 5;
- }
unsigned getCSRFirstUseCost(const MachineFunction &MF) const override {
// The cost of 2 means push and pop for each CSR.
return 2;
}
+ unsigned getCSRCostScale(const MachineFunction &MF) const {
+ return 100;
+ }
+
const TargetRegisterClass *
getSubClassWithSubReg(const TargetRegisterClass *RC,
unsigned Idx) const override;
>From ef045b71b3bc3618827820717b768d595a6daf11 Mon Sep 17 00:00:00 2001
From: Shreeyash Pandey <shrpand at qti.qualcomm.com>
Date: Wed, 26 Aug 2026 07:15:12 +0000
Subject: [PATCH 2/3] rebase
Signed-off-by: Shreeyash Pandey <shrpand at qti.qualcomm.com>
---
llvm/lib/Target/AArch64/AArch64RegisterInfo.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
index 7fdbf1b04439c..5b2312fbb80e1 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.h
@@ -59,7 +59,7 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
return 2;
}
- unsigned getCSRCostScale(const MachineFunction &MF) const {
+ unsigned getCSRCostScale(const MachineFunction &MF) const override {
return 100;
}
>From b52ca02d8c4e86200dcf022a0bd9f020eabd97d0 Mon Sep 17 00:00:00 2001
From: Shreeyash Pandey <shrpand at qti.qualcomm.com>
Date: Wed, 26 Aug 2026 07:16:50 +0000
Subject: [PATCH 3/3] restore global csr cost scale back to 80
Signed-off-by: Shreeyash Pandey <shrpand at qti.qualcomm.com>
---
llvm/lib/CodeGen/RegAllocGreedy.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 702088823417f..d534a71a38d0d 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -118,7 +118,7 @@ CSRFirstTimeCost("regalloc-csr-first-time-cost",
static cl::opt<unsigned> CSRCostScale(
"regalloc-csr-cost-scale",
cl::desc("Scale for the callee-saved register cost, in percentage."),
- cl::init(90), cl::Hidden);
+ cl::init(80), cl::Hidden);
static cl::opt<unsigned long> GrowRegionComplexityBudget(
"grow-region-complexity-budget",
More information about the llvm-commits
mailing list