[llvm] [AMDGPU][CodeGen] Incrementally update reserved regs for SIPreAllocateWWMRegs pass in RegisterClassInfo (PR #212201)

[Nikhil Kotikalapudi via llvm-commits]

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@@ -203,7 +264,6 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
   const TargetRegisterClass *RC = TRI->getLargestRegClassForRegPressureSet(Idx);
   assert(RC && "Failed to find register class");
-  compute(RC);
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nkotikal wrote:

Yep, dependent on mismatch in RegisterClassInfo::Tag vs specific RCInfo class tags.

https://github.com/llvm/llvm-project/pull/212201