[llvm] [SelectionDAG] Avoid irregular INSERT_SUBVECTOR when widening CTTZ_ELTS (PR #218019)

[Oscar Priego via llvm-commits]

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@@ -8722,7 +8722,19 @@ SDValue DAGTypeLegalizer::WidenVecOp_CttzElements(SDNode *N) {
     // Pad the widened portion with all-ones so the extra lanes appear as
     // active (non-zero) elements and do not contribute trailing zeros.
     SDValue AllOnes = DAG.getAllOnesConstant(DL, WideVT);
-    WideSource = DAG.getInsertSubvector(DL, AllOnes, Source, 0);
+    if (WideVT.isFixedLengthVector() &&
+        SourceVT.getVectorElementType() == MVT::i1 &&
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Opriego wrote:

Removed the MVT::i1 restriction; the existing X86 regression test still passes locally with assertions enabled.

https://github.com/llvm/llvm-project/pull/218019