[llvm] [AMDGPU] Track buffer resource num_records width in a subtarget field (PR #217136)
Krzysztof Drewniak via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 25 08:05:57 PDT 2026
https://github.com/krzysz00 updated https://github.com/llvm/llvm-project/pull/217136
>From 048ff2b85395239bd50afdec4c408c09049985a1 Mon Sep 17 00:00:00 2001
From: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: Tue, 18 Aug 2026 19:20:43 +0000
Subject: [PATCH 1/2] [AMDGPU] Track buffer resource num_records width in a
subtarget field
Replace the boolean 45-bit-num-records-buffer-resource subtarget
feature's `Has45BitNumRecordsBufferResource` flag with a numeric
`BufferResourceNumRecordsWidth` field.
AI disclosure: Code by Claude, comments and wordings by me
---
llvm/lib/Target/AMDGPU/AMDGPU.td | 36 ++++++++++++-------
.../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 2 +-
.../AMDGPU/AMDGPULowerBufferFatPointers.cpp | 2 +-
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 13 +++++++
llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 +-
5 files changed, 40 insertions(+), 15 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 160e91cb0da66..113ac2e12dbf6 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1532,11 +1532,17 @@ defm LdsBarrierArriveAtomic : AMDGPUSubtargetFeature<"lds-barrier-arrive-atomic"
"Has LDS barrier-arrive atomic instructions"
>;
-defm 45BitNumRecordsBufferResource : AMDGPUSubtargetFeature<"45-bit-num-records-buffer-resource",
- "The buffer resource (V#) supports 45-bit num_records",
- /*GenPredicate=*/0
+// The width of the num_records field of the buffer resource (V#).
+class FeatureNumRecordsBufferResource<int width> : SubtargetFeature<
+ !cast<string>(width)#"-bit-num-records-buffer-resource",
+ "BufferResourceNumRecordsWidth",
+ !cast<string>(width),
+ "The buffer resource (V#) has "#width#"-bit num_records"
>;
+def Feature32BitNumRecordsBufferResource : FeatureNumRecordsBufferResource<32>;
+def Feature45BitNumRecordsBufferResource : FeatureNumRecordsBufferResource<45>;
+
defm Clusters : AMDGPUSubtargetFeature<"clusters",
"Has clusters of workgroups support",
/*GenPredicate=*/0
@@ -1584,7 +1590,7 @@ def FeatureSouthernIslands : GCNSubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
FeatureVmemWriteVgprInOrder, FeatureCubeInsts, FeatureLerpInst,
FeatureSadInsts, FeatureMsadInsts, FeatureMqsadPkInsts,
FeatureCvtPkNormVOP2Insts, FeatureDX10ClampAndIEEEMode, FeatureMTBUFInsts,
- FeatureFormattedMUBUFInsts
+ FeatureFormattedMUBUFInsts, Feature32BitNumRecordsBufferResource
]
>;
@@ -1602,7 +1608,8 @@ def FeatureSeaIslands : GCNSubtargetFeatureGeneration<"SEA_ISLANDS",
FeatureSadInsts, FeatureQsadInsts, FeatureMsadInsts, FeatureMqsadPkInsts,
FeatureMqsadInsts, FeatureCvtPkNormVOP2Insts,
FeatureDX10ClampAndIEEEMode, FeatureInstCacheLineSize64,
- FeatureMTBUFInsts, FeatureFormattedMUBUFInsts
+ FeatureMTBUFInsts, FeatureFormattedMUBUFInsts,
+ Feature32BitNumRecordsBufferResource
]
>;
@@ -1623,7 +1630,8 @@ def FeatureVolcanicIslands : GCNSubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
FeatureLerpInst, FeatureSadInsts, FeatureQsadInsts, FeatureMsadInsts,
FeatureMqsadPkInsts, FeatureMqsadInsts,
FeatureCvtPkNormVOP2Insts, FeatureDX10ClampAndIEEEMode,
- FeatureInstCacheLineSize64, FeatureMTBUFInsts, FeatureFormattedMUBUFInsts
+ FeatureInstCacheLineSize64, FeatureMTBUFInsts, FeatureFormattedMUBUFInsts,
+ Feature32BitNumRecordsBufferResource
]
>;
@@ -1647,7 +1655,8 @@ def FeatureGFX9 : GCNSubtargetFeatureGeneration<"GFX9",
FeatureMsadInsts, FeatureMqsadPkInsts, FeatureMqsadInsts,
FeatureCvtNormInsts, FeatureCvtPkNormVOP2Insts,
FeatureCvtPkNormVOP3Insts, FeatureDX10ClampAndIEEEMode,
- FeatureInstCacheLineSize64, FeatureMTBUFInsts, FeatureFormattedMUBUFInsts
+ FeatureInstCacheLineSize64, FeatureMTBUFInsts, FeatureFormattedMUBUFInsts,
+ Feature32BitNumRecordsBufferResource
]
>;
@@ -1679,7 +1688,8 @@ def FeatureGFX10 : GCNSubtargetFeatureGeneration<"GFX10",
FeatureMqsadPkInsts, FeatureMqsadInsts,
FeatureCvtNormInsts, FeatureCvtPkNormVOP2Insts,
FeatureCvtPkNormVOP3Insts, FeatureDX10ClampAndIEEEMode, FeatureFlatOffsetBits12,
- FeatureInstCacheLineSize64, FeatureMTBUFInsts, FeatureFormattedMUBUFInsts
+ FeatureInstCacheLineSize64, FeatureMTBUFInsts, FeatureFormattedMUBUFInsts,
+ Feature32BitNumRecordsBufferResource
]
>;
@@ -1710,7 +1720,8 @@ def FeatureGFX11 : GCNSubtargetFeatureGeneration<"GFX11",
FeatureSadInsts, FeatureQsadInsts, FeatureMsadInsts, FeatureMqsadPkInsts,
FeatureMqsadInsts, FeatureCvtNormInsts,
FeatureCvtPkNormVOP2Insts, FeatureCvtPkNormVOP3Insts,
- FeatureInstCacheLineSize128, FeatureMTBUFInsts, FeatureFormattedMUBUFInsts
+ FeatureInstCacheLineSize128, FeatureMTBUFInsts, FeatureFormattedMUBUFInsts,
+ Feature32BitNumRecordsBufferResource
]
>;
@@ -1738,7 +1749,8 @@ def FeatureGFX12 : GCNSubtargetFeatureGeneration<"GFX12",
FeatureIEEEMinimumMaximumInsts, FeatureSALUMinimumMaximumInsts,
FeatureMinimum3Maximum3F32, FeatureMinimum3Maximum3F16,
FeatureAgentScopeFineGrainedRemoteMemoryAtomics, FeatureFlatOffsetBits24,
- FeatureFlatSignedOffset, FeatureInstCacheLineSize128
+ FeatureFlatSignedOffset, FeatureInstCacheLineSize128,
+ Feature32BitNumRecordsBufferResource
]
>;
@@ -1768,7 +1780,8 @@ def FeatureGFX13 : GCNSubtargetFeatureGeneration<"GFX13",
FeatureMinimum3Maximum3F32, FeatureMinimum3Maximum3F16,
FeatureAgentScopeFineGrainedRemoteMemoryAtomics, FeatureFlatOffsetBits24,
FeatureFlatSignedOffset, FeatureInstCacheLineSize128,
- FeatureMTBUFInsts, FeatureFormattedMUBUFInsts
+ FeatureMTBUFInsts, FeatureFormattedMUBUFInsts,
+ Feature45BitNumRecordsBufferResource
]
>;
//===----------------------------------------------------------------------===//
@@ -2494,7 +2507,6 @@ def FeatureISAVersion13 : FeatureSet<
FeatureSALUFloatInsts,
FeaturePseudoScalarTrans,
FeatureRestrictedSOffset,
- Feature45BitNumRecordsBufferResource,
FeatureScalarDwordx3Loads,
FeatureDPPSrc1SGPR,
FeatureBitOp3Insts,
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 42048a9bb3105..7c1a26f761c96 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -6398,7 +6398,7 @@ bool AMDGPULegalizerInfo::legalizePointerAsRsrcIntrin(
auto ExtStride = B.buildAnyExt(I32, Stride);
- if (ST.has45BitNumRecordsBufferResource()) {
+ if (ST.getBufferResourceNumRecordsWidth() == 45) {
NumRecords = B.buildZExtOrTrunc(I64, NumRecords).getReg(0);
NumRecords =
B.buildAnd(I64, NumRecords, B.buildConstant(I64, (1ULL << 45) - 1))
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
index 55938fe352519..236d8e619a5ec 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
@@ -892,7 +892,7 @@ LegalizeBufferContentTypesVisitor::analyzeOobProperties(Value *Ptr, Type *Ty,
Result.NoPartialOOB = true;
const SCEV *BoundsDiff;
- if (ST->has45BitNumRecordsBufferResource()) {
+ if (ST->getBufferResourceNumRecordsWidth() == 45) {
const SCEV *PtrDiffExt =
SE->getNoopOrZeroExtend(PtrDiff, NumRecords->getType());
BoundsDiff = SE->getMinusSCEV(NumRecords, PtrDiffExt);
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 4287836b06226..bb98c2b1fa3b5 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -23,6 +23,7 @@
#include "Utils/AMDGPUBaseInfo.h"
#include "llvm/Support/AMDHSAKernelDescriptor.h"
#include "llvm/Support/ErrorHandling.h"
+#include <optional>
#define GET_SUBTARGETINFO_HEADER
#include "AMDGPUGenSubtargetInfo.inc"
@@ -83,6 +84,10 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
// Data (VMEM) cache line size in bytes; set from TableGen subtarget features.
unsigned DataCacheLineSize = 0;
+ /// The width, in bits, of the num_records field of a buffer resource (V#),
+ /// set from tablegen subtarget features, 0 is unknown.
+ unsigned BufferResourceNumRecordsWidth = 0;
+
// Dynamically set bits that enable features.
bool ScalarizeGlobal = false;
const bool BufferOOBRelaxed;
@@ -351,6 +356,14 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool hasRelaxedBufferOOBMode() const { return BufferOOBRelaxed; }
bool hasRelaxedTBufferOOBMode() const { return TBufferOOBRelaxed; }
+ /// Return the width, in bits, of the num_records field of a buffer resource
+ /// (V#) on this subtarget, or std::nullopt if not yet knows.
+ std::optional<unsigned> getBufferResourceNumRecordsWidth() const {
+ if (BufferResourceNumRecordsWidth == 0)
+ return std::nullopt;
+ return BufferResourceNumRecordsWidth;
+ }
+
bool isCuModeEnabled() const { return EnableCuMode; }
bool isPreciseMemoryEnabled() const { return EnablePreciseMemory; }
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 15053568da8dc..96e0def779423 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -13276,7 +13276,7 @@ SDValue SITargetLowering::lowerPointerAsRsrcIntrin(SDNode *Op,
SDValue ExtStride = DAG.getAnyExtOrTrunc(Stride, Loc, MVT::i32);
SDValue Rsrc;
- if (Subtarget->has45BitNumRecordsBufferResource()) {
+ if (Subtarget->getBufferResourceNumRecordsWidth() == 45) {
NumRecords = DAG.getZExtOrTrunc(NumRecords, Loc, MVT::i64);
NumRecords = DAG.getNode(ISD::AND, Loc, MVT::i64, NumRecords,
DAG.getConstant((1ULL << 45) - 1, Loc, MVT::i64));
>From 0f4583427c3b76176d5722ffb20794b3a36db3d8 Mon Sep 17 00:00:00 2001
From: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: Tue, 25 Aug 2026 00:42:49 -0500
Subject: [PATCH 2/2] Fix typo
Co-authored-by: Lukas Sommer <lukas.sommer at amd.com>
---
llvm/lib/Target/AMDGPU/GCNSubtarget.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index bb98c2b1fa3b5..e7e2f2d331649 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -357,7 +357,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool hasRelaxedTBufferOOBMode() const { return TBufferOOBRelaxed; }
/// Return the width, in bits, of the num_records field of a buffer resource
- /// (V#) on this subtarget, or std::nullopt if not yet knows.
+ /// (V#) on this subtarget, or std::nullopt if not yet known.
std::optional<unsigned> getBufferResourceNumRecordsWidth() const {
if (BufferResourceNumRecordsWidth == 0)
return std::nullopt;
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