[llvm] [X86] Lower bf16->f32/f64 fpext without a GPR round-trip (PR #218359)

[Phoebe Wang via llvm-commits]

================
@@ -62476,6 +62511,15 @@ static SDValue combineSCALAR_TO_VECTOR(SDNode *N, SelectionDAG &DAG,
     // Combine (v2i64 (scalar_to_vector (i64 (bitcast (mmx))))) to MOVQ2DQ.
     if (VT == MVT::v2i64 && SrcOp.getValueType() == MVT::x86mmx)
       return DAG.getNode(X86ISD::MOVQ2DQ, DL, VT, SrcOp);
+    // Combine (v8i16 (scalar_to_vector (i16 (bitcast (f16/bf16))))) to VMOVW.
+    if (Subtarget.hasFP16() && VT == MVT::v8i16) {
----------------
phoebewang wrote:

Move `VT == MVT::v8i16` before `Subtarget.hasFP16()` as it's a bit cheaper

https://github.com/llvm/llvm-project/pull/218359