[llvm] 68f2756 - [AArch64][Atomics] Add test file for testing <1xTy> store atomics (#216028)

[via llvm-commits]

Author: Kieran B
Date: 2026-08-25T14:42:32+01:00
New Revision: 68f275666c9984e07d147a3cff3ddda012a80ad3

URL: https://github.com/llvm/llvm-project/commit/68f275666c9984e07d147a3cff3ddda012a80ad3
DIFF: https://github.com/llvm/llvm-project/commit/68f275666c9984e07d147a3cff3ddda012a80ad3.diff

LOG: [AArch64][Atomics] Add test file for testing <1xTy> store atomics (#216028)

Currently, there exists no testing for <1xTy> store atomic.
These used to throw a widening legalization error but was fixed due to
this [PR](https://github.com/llvm/llvm-project/pull/197618)
Add these tests for AArch64 to ensure regression does not occur.

Note: Currently <1xi64> has a instruction selection issue and this is
why it has not been added.
A future patch will fix this case.

Added: 
    llvm/test/CodeGen/AArch64/atomic-vector-store.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AArch64/atomic-vector-store.ll b/llvm/test/CodeGen/AArch64/atomic-vector-store.ll
new file mode 100644
index 0000000000000..e0e7611d1db5b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/atomic-vector-store.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -global-isel=0 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -global-isel=1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+define void @test_store_release_v1i8(ptr %ptr, <1 x i8> %data) nounwind {
+; CHECK-LABEL: test_store_release_v1i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    umov w8, v0.b[0]
+; CHECK-NEXT:    stlrb w8, [x0]
+; CHECK-NEXT:    ret
+  store atomic <1 x i8> %data, ptr %ptr release, align 1
+  ret void
+}
+
+define void @test_store_monotonic_v1i16(ptr %ptr, <1 x i16> %data) nounwind {
+; CHECK-SD-LABEL: test_store_monotonic_v1i16:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT:    umov w8, v0.h[0]
+; CHECK-SD-NEXT:    strh w8, [x0]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_store_monotonic_v1i16:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    str h0, [x0]
+; CHECK-GI-NEXT:    ret
+  store atomic <1 x i16> %data, ptr %ptr monotonic, align 2
+  ret void
+}
+
+define void @test_store_seq_cst_v1i32(ptr %ptr, <1 x i32> %data) nounwind {
+; CHECK-SD-LABEL: test_store_seq_cst_v1i32:
+; CHECK-SD:       // %bb.0:
+; CHECK-SD-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT:    fmov w8, s0
+; CHECK-SD-NEXT:    stlr w8, [x0]
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: test_store_seq_cst_v1i32:
+; CHECK-GI:       // %bb.0:
+; CHECK-GI-NEXT:    fmov w8, s0
+; CHECK-GI-NEXT:    stlr w8, [x0]
+; CHECK-GI-NEXT:    ret
+  store atomic <1 x i32> %data, ptr %ptr seq_cst, align 4
+  ret void
+}