[llvm] 013ab33 - [X86] Allow disjoint ors in combineAddOrSubToADCOrSBB (#218410)

[via llvm-commits]

Author: AZero13
Date: 2026-08-25T11:02:38+01:00
New Revision: 013ab338470356f0aa15b820c73a07a3a3e54493

URL: https://github.com/llvm/llvm-project/commit/013ab338470356f0aa15b820c73a07a3a3e54493
DIFF: https://github.com/llvm/llvm-project/commit/013ab338470356f0aa15b820c73a07a3a3e54493.diff

LOG: [X86] Allow disjoint ors in combineAddOrSubToADCOrSBB (#218410)

This allows folding ORs to ADC.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/combine-adc.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 6d83fb8052ed3..30da28afd4156 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -53650,6 +53650,9 @@ static SDValue combineAddOrSubToADCOrSBB(SDNode *N, const SDLoc &DL,
   SDValue Y = N->getOperand(1);
   EVT VT = N->getValueType(0);
 
+  if (N->getOpcode() == ISD::OR && !N->getFlags().hasDisjoint())
+    return SDValue();
+
   if (SDValue ADCOrSBB = combineAddOrSubToADCOrSBB(IsSub, DL, VT, X, Y, DAG))
     return ADCOrSBB;
 
@@ -53941,6 +53944,9 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
   if (SDValue R = combineOrWithGF2P8AFFINEQB(N, dl, DAG, VT))
     return R;
 
+  if (SDValue R = combineAddOrSubToADCOrSBB(N, dl, DAG))
+    return R;
+
   return SDValue();
 }
 

diff  --git a/llvm/test/CodeGen/X86/combine-adc.ll b/llvm/test/CodeGen/X86/combine-adc.ll
index cb934c8664e45..df20563489bc3 100644
--- a/llvm/test/CodeGen/X86/combine-adc.ll
+++ b/llvm/test/CodeGen/X86/combine-adc.ll
@@ -249,5 +249,50 @@ define i32 @adc_add_multi_use(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, ptr %5) no
   ret i32 %13
 }
 
+
+define i32 @adc_shl(i32 %a, i32 %b) {
+; X86-LABEL: adc_shl:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    addl %eax, %eax
+; X86-NEXT:    cmpl $70, {{[0-9]+}}(%esp)
+; X86-NEXT:    adcl $0, %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: adc_shl:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    leal (%rdi,%rdi), %eax
+; X64-NEXT:    cmpl $70, %esi
+; X64-NEXT:    adcl $0, %eax
+; X64-NEXT:    retq
+  %add = shl i32 %a, 1
+  %cmp = icmp ult i32 %b, 70
+  %conv = zext i1 %cmp to i32
+  %add1 = or disjoint i32 %add, %conv
+  ret i32 %add1
+}
+
+define i32 @adc_test(i32 %a, i32 %b) {
+; X86-LABEL: adc_test:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    cmpl $70, {{[0-9]+}}(%esp)
+; X86-NEXT:    adcl %eax, %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: adc_test:
+; X64:       # %bb.0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    cmpl $70, %esi
+; X64-NEXT:    adcl %edi, %eax
+; X64-NEXT:    retq
+  %add = add i32 %a, %a
+  %cmp = icmp ult i32 %b, 70
+  %conv = zext i1 %cmp to i32
+  %add1 = add i32 %add, %conv
+  ret i32 %add1
+}
+
 declare { i8, i32 } @llvm.x86.addcarry.32(i8, i32, i32)
 declare void @use(i8)