[llvm] [AMDGPU] MC support for indexed VBUFFER resources for gfx13 (PR #218649)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 25 02:47:33 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: sstipano
<details>
<summary>Changes</summary>
---
Patch is 64.33 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/218649.diff
14 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPU.td (+5)
- (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (+32)
- (modified) llvm/lib/Target/AMDGPU/BUFInstructions.td (+163-111)
- (modified) llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (+29-1)
- (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp (+12)
- (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h (+2)
- (modified) llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp (+20)
- (modified) llvm/lib/Target/AMDGPU/SIRegisterInfo.td (+26)
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (+4)
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (+4)
- (modified) llvm/test/MC/AMDGPU/gfx13_asm_vbuffer_mtbuf.s (+9)
- (modified) llvm/test/MC/AMDGPU/gfx13_asm_vbuffer_mubuf.s (+64)
- (added) llvm/test/MC/AMDGPU/gfx13_asm_vbuffer_mubuf_err.s (+16)
- (modified) llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected (+2-2)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 160e91cb0da66..7f99406f4f54f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -966,6 +966,10 @@ defm CubeInsts : AMDGPUSubtargetFeature<"cube-insts",
"Has v_cube* instructions"
>;
+defm IndexedResources : AMDGPUSubtargetFeature<"indexed-resources",
+ "Has indexed resources"
+>;
+
defm LerpInst : AMDGPUSubtargetFeature<"lerp-inst",
"Has v_lerp_u8 instruction"
>;
@@ -2531,6 +2535,7 @@ def FeatureISAVersion13 : FeatureSet<
FeatureCvtPkNormVOP3Insts,
FeatureSmemPrefetchInsts,
FeatureAsyncLoadToLDSInsts,
+ FeatureIndexedResources
]>;
def FeatureISAVersion13_Generic: FeatureSet<
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 9ae621fdc6b71..94dfe21a41c1c 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -343,6 +343,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isVReg32OrOff() const { return isOff() || isVReg32(); }
+ bool isRsrcReg32() const { return isRegClass(AMDGPU::RsrcReg32RegClassID); }
+
bool isNull() const { return isRegKind() && getReg() == AMDGPU::SGPR_NULL; }
bool isAV_LdSt_32_Align2_RegOp() const {
@@ -1706,6 +1708,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool AllowImm = true);
ParseStatus parseRegWithFPInputMods(OperandVector &Operands);
ParseStatus parseRegWithIntInputMods(OperandVector &Operands);
+ ParseStatus parseRsrcReg(OperandVector &Operands);
ParseStatus parseVReg32OrOff(OperandVector &Operands);
ParseStatus tryParseIndexKey(OperandVector &Operands,
AMDGPUOperand::ImmTy ImmTy);
@@ -3600,6 +3603,35 @@ ParseStatus AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) {
return parseRegOrImmWithIntInputMods(Operands, false);
}
+ParseStatus AMDGPUAsmParser::parseRsrcReg(OperandVector &Operands) {
+ // Without the marker, fall back to plain register parsing so the legacy
+ // bare-register form (e.g. `s8`, `v8`) still assembles for indexed
+ // buffer/image instructions.
+ if (!trySkipId("rsrcidx"))
+ return parseReg(Operands);
+
+ if (!skipToken(AsmToken::LParen, "expected left paren after rsrcidx"))
+ return ParseStatus::Failure;
+
+ SMLoc RegLoc = getLoc();
+ std::unique_ptr<AMDGPUOperand> Reg = parseRegister();
+ if (!Reg)
+ return ParseStatus::Failure;
+
+ // Enforce that the inner register is a valid index register. The matcher
+ // predicate alone is not sufficient: if it fails, the matcher will fall back
+ // to a non-indexed instruction variant whose resource operand happens to
+ // accept the same register, silently dropping the `rsrcidx` intent.
+ if (!Reg->isRsrcReg32())
+ return Error(RegLoc, "rsrcidx operand must be a 32-bit SGPR or VGPR");
+
+ if (!skipToken(AsmToken::RParen, "expected closing parenthesis"))
+ return ParseStatus::Failure;
+
+ Operands.push_back(std::move(Reg));
+ return ParseStatus::Success;
+}
+
ParseStatus AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {
auto Loc = getLoc();
if (trySkipId("off")) {
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index 5faa478407c34..2175772b00b89 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -54,6 +54,7 @@ class BUF_Pseudo <string opName, dag outs, dag ins,
InstSI<outs, ins, "", pattern>,
SIMCInstr<opName, SIEncodingFamily.NONE> {
+ bit isIndexed = 0;
let isPseudo = 1;
let isCodeGenOnly = 1;
let Size = 8;
@@ -159,14 +160,15 @@ class MTBUF_Real <MTBUF_Pseudo ps, string real_name = ps.Mnemonic> :
}
class getMTBUFInsDA<list<RegisterOperand> vdataList,
- list<RegisterOperand> vaddrList=[], bit hasRestrictedSOffset> {
+ list<RegisterOperand> vaddrList=[], bit hasRestrictedSOffset,
+ DAGOperand RsrcRC = SReg_128_XNULL> {
RegisterOperand vdata_op = !if(!empty(vdataList), ?, !head(vdataList));
RegisterOperand vaddr_op = !if(!empty(vaddrList), ?, !head(vaddrList));
dag SOffset = !if(hasRestrictedSOffset, (ins SReg_32:$soffset),
(ins SCSrc_b32:$soffset));
- dag NonVaddrInputs = !con((ins SReg_128_XNULL:$srsrc), SOffset,
+ dag NonVaddrInputs = !con((ins RsrcRC:$srsrc), SOffset,
(ins Offset:$offset, FORMAT:$format, CPol_0:$cpol, i1imm_0:$swz));
dag Inputs = !if(!empty(vaddrList),
@@ -177,13 +179,13 @@ class getMTBUFInsDA<list<RegisterOperand> vdataList,
!con((ins vdata_op:$vdata), Inputs));
}
-class getMTBUFIns<int addrKind, list<RegisterOperand> vdataList=[], bit hasRestrictedSOffset> {
+class getMTBUFIns<int addrKind, list<RegisterOperand> vdataList=[], bit hasRestrictedSOffset, DAGOperand RsrcRC = SReg_128_XNULL> {
dag ret =
- !if(!eq(addrKind, BUFAddrKind.Offset), getMTBUFInsDA<vdataList, [], hasRestrictedSOffset>.ret,
- !if(!eq(addrKind, BUFAddrKind.OffEn), getMTBUFInsDA<vdataList, [VGPROp_32], hasRestrictedSOffset>.ret,
- !if(!eq(addrKind, BUFAddrKind.IdxEn), getMTBUFInsDA<vdataList, [VGPROp_32], hasRestrictedSOffset>.ret,
- !if(!eq(addrKind, BUFAddrKind.BothEn), getMTBUFInsDA<vdataList, [VGPROp_64], hasRestrictedSOffset>.ret,
- !if(!eq(addrKind, BUFAddrKind.Addr64), getMTBUFInsDA<vdataList, [VGPROp_64], hasRestrictedSOffset>.ret,
+ !if(!eq(addrKind, BUFAddrKind.Offset), getMTBUFInsDA<vdataList, [], hasRestrictedSOffset, RsrcRC>.ret,
+ !if(!eq(addrKind, BUFAddrKind.OffEn), getMTBUFInsDA<vdataList, [VGPROp_32], hasRestrictedSOffset, RsrcRC>.ret,
+ !if(!eq(addrKind, BUFAddrKind.IdxEn), getMTBUFInsDA<vdataList, [VGPROp_32], hasRestrictedSOffset, RsrcRC>.ret,
+ !if(!eq(addrKind, BUFAddrKind.BothEn), getMTBUFInsDA<vdataList, [VGPROp_64], hasRestrictedSOffset, RsrcRC>.ret,
+ !if(!eq(addrKind, BUFAddrKind.Addr64), getMTBUFInsDA<vdataList, [VGPROp_64], hasRestrictedSOffset, RsrcRC>.ret,
(ins))))));
}
@@ -219,37 +221,40 @@ class MTBUF_Load_Pseudo <string opName,
RegisterOperand vdataClass,
int elems,
bit hasRestrictedSOffset = 0,
+ DAGOperand RsrcRC = SReg_128_XNULL,
list<dag> pattern=[]>
: MTBUF_Pseudo<opName,
(outs vdataClass:$vdata),
- getMTBUFIns<addrKind, [], hasRestrictedSOffset>.ret,
+ getMTBUFIns<addrKind, [], hasRestrictedSOffset, RsrcRC>.ret,
getMTBUFAsmOps<addrKind>.ret,
pattern>,
MTBUF_SetupAddr<addrKind> {
- let PseudoInstr = opName # "_" # getAddrName<addrKind>.ret;
+ let isIndexed = !ne(RsrcRC, SReg_128_XNULL);
+ defvar suffix = !if(isIndexed, "_indexed", "");
+ let PseudoInstr = opName # suffix # "_" # getAddrName<addrKind>.ret;
let mayLoad = 1;
let mayStore = 0;
let elements = elems;
}
multiclass MTBUF_Pseudo_Loads_Helper<string opName, RegisterOperand vdataClass,
- int elems, bit hasRestrictedSOffset> {
+ int elems, bit hasRestrictedSOffset, DAGOperand RsrcRC = SReg_128_XNULL> {
- def _OFFSET : MTBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, elems, hasRestrictedSOffset>,
+ def _OFFSET : MTBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, elems, hasRestrictedSOffset, RsrcRC>,
MTBUFAddr64Table<0, NAME>;
- def _ADDR64 : MTBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, vdataClass, elems, hasRestrictedSOffset>,
+ def _ADDR64 : MTBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, vdataClass, elems, hasRestrictedSOffset, RsrcRC>,
MTBUFAddr64Table<1, NAME>;
- def _OFFEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, elems, hasRestrictedSOffset>;
- def _IDXEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, elems, hasRestrictedSOffset>;
- def _BOTHEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, elems, hasRestrictedSOffset>;
+ def _OFFEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, elems, hasRestrictedSOffset, RsrcRC>;
+ def _IDXEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, elems, hasRestrictedSOffset, RsrcRC>;
+ def _BOTHEN : MTBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, elems, hasRestrictedSOffset, RsrcRC>;
let DisableWQM = 1 in {
- def _OFFSET_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, elems, hasRestrictedSOffset>;
- def _OFFEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, elems, hasRestrictedSOffset>;
- def _IDXEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, elems, hasRestrictedSOffset>;
- def _BOTHEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, elems, hasRestrictedSOffset>;
+ def _OFFSET_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.Offset, vdataClass, elems, hasRestrictedSOffset, RsrcRC>;
+ def _OFFEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, elems, hasRestrictedSOffset, RsrcRC>;
+ def _IDXEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, elems, hasRestrictedSOffset, RsrcRC>;
+ def _BOTHEN_exact : MTBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, elems, hasRestrictedSOffset, RsrcRC>;
}
}
@@ -257,6 +262,7 @@ multiclass MTBUF_Pseudo_Loads<string opName, RegisterOperand vdataClass,
int elems> {
defm NAME : MTBUF_Pseudo_Loads_Helper<opName, vdataClass, elems, 0>;
defm _VBUFFER : MTBUF_Pseudo_Loads_Helper<opName, vdataClass, elems, 1>;
+ defm _VBUFFER_indexed : MTBUF_Pseudo_Loads_Helper<opName, vdataClass, elems, 1, RsrcReg128Op>;
}
class MTBUF_Store_Pseudo <string opName,
@@ -264,37 +270,40 @@ class MTBUF_Store_Pseudo <string opName,
RegisterOperand vdataClass,
int elems,
bit hasRestrictedSOffset = 0,
+ DAGOperand RsrcRC = SReg_128_XNULL,
list<dag> pattern=[]>
: MTBUF_Pseudo<opName,
(outs),
- getMTBUFIns<addrKind, [vdataClass], hasRestrictedSOffset>.ret,
+ getMTBUFIns<addrKind, [vdataClass], hasRestrictedSOffset, RsrcRC>.ret,
getMTBUFAsmOps<addrKind>.ret,
pattern>,
MTBUF_SetupAddr<addrKind> {
- let PseudoInstr = opName # "_" # getAddrName<addrKind>.ret;
+ let isIndexed = !ne(RsrcRC, SReg_128_XNULL);
+ defvar suffix = !if(isIndexed, "_indexed", "");
+ let PseudoInstr = opName # suffix # "_" # getAddrName<addrKind>.ret;
let mayLoad = 0;
let mayStore = 1;
let elements = elems;
}
multiclass MTBUF_Pseudo_Stores_Helper<string opName, RegisterOperand vdataClass,
- int elems, bit hasRestrictedSOffset> {
+ int elems, bit hasRestrictedSOffset, DAGOperand RsrcRC = SReg_128_XNULL> {
- def _OFFSET : MTBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass, elems, hasRestrictedSOffset>,
+ def _OFFSET : MTBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass, elems, hasRestrictedSOffset, RsrcRC>,
MTBUFAddr64Table<0, NAME>;
- def _ADDR64 : MTBUF_Store_Pseudo <opName, BUFAddrKind.Addr64, vdataClass, elems, hasRestrictedSOffset>,
+ def _ADDR64 : MTBUF_Store_Pseudo <opName, BUFAddrKind.Addr64, vdataClass, elems, hasRestrictedSOffset, RsrcRC>,
MTBUFAddr64Table<1, NAME>;
- def _OFFEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, elems, hasRestrictedSOffset>;
- def _IDXEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, elems, hasRestrictedSOffset>;
- def _BOTHEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, elems, hasRestrictedSOffset>;
+ def _OFFEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, elems, hasRestrictedSOffset, RsrcRC>;
+ def _IDXEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, elems, hasRestrictedSOffset, RsrcRC>;
+ def _BOTHEN : MTBUF_Store_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, elems, hasRestrictedSOffset, RsrcRC>;
let DisableWQM = 1 in {
- def _OFFSET_exact : MTBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass, elems, hasRestrictedSOffset>;
- def _OFFEN_exact : MTBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, elems, hasRestrictedSOffset>;
- def _IDXEN_exact : MTBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, elems, hasRestrictedSOffset>;
- def _BOTHEN_exact : MTBUF_Store_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, elems, hasRestrictedSOffset>;
+ def _OFFSET_exact : MTBUF_Store_Pseudo <opName, BUFAddrKind.Offset, vdataClass, elems, hasRestrictedSOffset, RsrcRC>;
+ def _OFFEN_exact : MTBUF_Store_Pseudo <opName, BUFAddrKind.OffEn, vdataClass, elems, hasRestrictedSOffset, RsrcRC>;
+ def _IDXEN_exact : MTBUF_Store_Pseudo <opName, BUFAddrKind.IdxEn, vdataClass, elems, hasRestrictedSOffset, RsrcRC>;
+ def _BOTHEN_exact : MTBUF_Store_Pseudo <opName, BUFAddrKind.BothEn, vdataClass, elems, hasRestrictedSOffset, RsrcRC>;
}
}
@@ -302,6 +311,7 @@ multiclass MTBUF_Pseudo_Stores<string opName, RegisterOperand vdataClass,
int elems> {
defm NAME : MTBUF_Pseudo_Stores_Helper<opName, vdataClass, elems, 0>;
defm _VBUFFER : MTBUF_Pseudo_Stores_Helper<opName, vdataClass, elems, 1>;
+ defm _VBUFFER_indexed : MTBUF_Pseudo_Stores_Helper<opName, vdataClass, elems, 1, RsrcReg128Op>;
}
//===----------------------------------------------------------------------===//
@@ -418,14 +428,14 @@ class getBUFVDataRegisterOperandForOp<RegisterOperand Op, bit isTFE> {
class getMUBUFInsDA<list<RegisterOperand> vdataList,
list<RegisterOperand> vaddrList, bit isTFE, bit hasRestrictedSOffset,
- bit isTrue16, bit isLds> {
+ bit isTrue16, bit isLds, DAGOperand RsrcRC = SReg_128_XNULL> {
RegisterOperand vdataClass = !if(!empty(vdataList), ?, !head(vdataList));
RegisterOperand vaddr_op = !if(!empty(vaddrList), ?, !head(vaddrList));
RegisterOperand vdata_op = getBUFVDataRegisterOperand<!cast<SIRegisterClassLike>(vdataClass.RegClass).Size, isTFE, isTrue16>.ret;
dag SOffset = !if(hasRestrictedSOffset, (ins SReg_32:$soffset), (ins SCSrc_b32:$soffset));
dag IsAsyncOpnd = !if(isLds, (ins i1imm_0:$IsAsync), (ins));
- dag NonVaddrInputs = !con((ins SReg_128_XNULL:$srsrc), SOffset, (ins Offset:$offset, CPol_0:$cpol, i1imm_0:$swz), IsAsyncOpnd);
+ dag NonVaddrInputs = !con((ins RsrcRC:$srsrc), SOffset, (ins Offset:$offset, CPol_0:$cpol, i1imm_0:$swz), IsAsyncOpnd);
dag Inputs = !if(!empty(vaddrList), NonVaddrInputs, !con((ins vaddr_op:$vaddr), NonVaddrInputs));
dag ret = !if(!empty(vdataList), Inputs, !con((ins vdata_op:$vdata), Inputs));
@@ -451,13 +461,13 @@ class getMUBUFElements<ValueType vt> {
}
class getMUBUFIns<int addrKind, list<RegisterOperand> vdataList, bit isTFE,
- bit hasRestrictedSOffset, bit isTrue16, bit isLds> {
+ bit hasRestrictedSOffset, bit isTrue16, bit isLds, DAGOperand RsrcRC = SReg_128_XNULL> {
dag ret =
- !if(!eq(addrKind, BUFAddrKind.Offset), getMUBUFInsDA<vdataList, [], isTFE, hasRestrictedSOffset, isTrue16, isLds>.ret,
- !if(!eq(addrKind, BUFAddrKind.OffEn), getMUBUFInsDA<vdataList, [VGPROp_32], isTFE, hasRestrictedSOffset, isTrue16, isLds>.ret,
- !if(!eq(addrKind, BUFAddrKind.IdxEn), getMUBUFInsDA<vdataList, [VGPROp_32], isTFE, hasRestrictedSOffset, isTrue16, isLds>.ret,
- !if(!eq(addrKind, BUFAddrKind.BothEn), getMUBUFInsDA<vdataList, [VGPROp_64], isTFE, hasRestrictedSOffset, isTrue16, isLds>.ret,
- !if(!eq(addrKind, BUFAddrKind.Addr64), getMUBUFInsDA<vdataList, [VGPROp_64], isTFE, hasRestrictedSOffset, isTrue16, isLds>.ret,
+ !if(!eq(addrKind, BUFAddrKind.Offset), getMUBUFInsDA<vdataList, [], isTFE, hasRestrictedSOffset, isTrue16, isLds, RsrcRC>.ret,
+ !if(!eq(addrKind, BUFAddrKind.OffEn), getMUBUFInsDA<vdataList, [VGPROp_32], isTFE, hasRestrictedSOffset, isTrue16, isLds, RsrcRC>.ret,
+ !if(!eq(addrKind, BUFAddrKind.IdxEn), getMUBUFInsDA<vdataList, [VGPROp_32], isTFE, hasRestrictedSOffset, isTrue16, isLds, RsrcRC>.ret,
+ !if(!eq(addrKind, BUFAddrKind.BothEn), getMUBUFInsDA<vdataList, [VGPROp_64], isTFE, hasRestrictedSOffset, isTrue16, isLds, RsrcRC>.ret,
+ !if(!eq(addrKind, BUFAddrKind.Addr64), getMUBUFInsDA<vdataList, [VGPROp_64], isTFE, hasRestrictedSOffset, isTrue16, isLds, RsrcRC>.ret,
(ins))))));
}
@@ -498,16 +508,19 @@ class MUBUF_Load_Pseudo <string opName,
bit isLdsOpc = 0,
bit isTFE = 0,
bit hasRestrictedSOffset = 0,
+ DAGOperand RsrcRC = SReg_128_XNULL,
list<dag> pattern=[],
RegisterOperand vdata_op = getBUFVDataRegisterOperand<vdata_vt.Size, isTFE>.ret>
: MUBUF_Pseudo<opName,
!if(!or(isLds, isLdsOpc), (outs), (outs vdata_op:$vdata)),
- !con(getMUBUFIns<addrKind, [], isTFE, hasRestrictedSOffset, 0, isLds>.ret,
+ !con(getMUBUFIns<addrKind, [], isTFE, hasRestrictedSOffset, 0, isLds, RsrcRC>.ret,
!if(HasTiedDest, (ins vdata_op:$vdata_in), (ins))),
getMUBUFAsmOps<addrKind, !or(isLds, isLdsOpc), isLds, isTFE>.ret,
pattern>,
MUBUF_SetupAddr<addrKind> {
- let PseudoInstr = opName # !if(isLds, "_lds", "") # !if(isTFE, "_tfe", "") #
+ let isIndexed = !ne(RsrcRC, SReg_128_XNULL);
+ defvar suffix = !if(isIndexed, "_indexed", "");
+ let PseudoInstr = opName # suffix # !if(isLds, "_lds", "") # !if(isTFE, "_tfe", "") #
"_" # getAddrName<addrKind>.ret;
let AsmMatchConverter = "cvtMubuf";
@@ -548,50 +561,50 @@ multiclass MUBUF_Pseudo_Load_Pats<string BaseInst, ValueType load_vt = i32, SDPa
}
multiclass MUBUF_Pseudo_Loads_Helper<string opName, ValueType load_vt,
- bit TiedDest, bit isLds, bit isTFE, bit hasRestrictedSOffset> {
+ bit TiedDest, bit isLds, bit isTFE, bit hasRestrictedSOffset, DAGOperand RsrcRC = SReg_128_XNULL> {
defvar legal_load_vt = !if(!eq(load_vt, v3f16), v4f16, load_vt);
- def _OFFSET : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, legal_load_vt, TiedDest, isLds, 0, isTFE, hasRestrictedSOffset>,
+ def _OFFSET : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, legal_load_vt, TiedDest, isLds, 0, isTFE, hasRestrictedSOffset, RsrcRC>,
MUBUFAddr64Table<0, NAME # !if(isLds, "_LDS", "")>;
- def _ADDR64 : MUBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, legal_load_vt, TiedDest, isLds, 0, isTFE, hasRestrictedSOffset>,
+ def _ADDR64 : MUBUF_Load_Pseudo <opName, BUFAddrKind.Addr64, legal_load_vt, TiedDest, isLds, 0, isTFE, hasRestrictedSOffset, RsrcRC>,
MUBUFAddr64Table<1, NAME # !if(isLds, "_LDS", "")>;
- def _OFFEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, legal_load_vt, TiedDest, isLds, 0, isTFE, hasRestrictedSOffset>;
- def _IDXEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, legal_load_vt, TiedDest, isLds, 0, isTFE, hasRestrictedSOffset>;
- def _BOTHEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, legal_load_vt, TiedDest, isLds, 0, isTFE, hasRestrictedSOffset>;
+ def _OFFEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, legal_load_vt, TiedDest, isLds, 0, isTFE, hasRestrictedSOffset, RsrcRC>;
+ def _IDXEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, legal_load_vt, TiedDest, isLds, 0, isTFE, hasRestrictedSOffset, RsrcRC>;
+ def _BOTHEN : MUBUF_Load_Pseudo <opName, BUFAddrKind.BothEn, legal_load_vt, TiedDest, isLds, 0, isTFE, hasRestrictedSOffset, RsrcRC>;
let DisableWQM = 1 in {
- def _OFFSET_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.Offset, legal_load_vt, TiedDest, isLds, 0, isTFE, hasRestrictedSOffset>;
- def _OFFEN_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.OffEn, legal_load_vt, TiedDest, isLds, 0, isTFE, hasRestrictedSOffset>;
- def _IDXEN_exact : MUBUF_Load_Pseudo <opName, BUFAddrKind.IdxEn, legal_load_vt, TiedD...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/218649
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