[llvm] [X86] Allow disjoint ors in combineAddOrSubToADCOrSBB (PR #218410)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Tue Aug 25 02:29:02 PDT 2026
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/218410
>From b9134dfbc76ec00bce5d2a8e21a5c729f8a66257 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Mon, 24 Aug 2026 09:14:23 -0400
Subject: [PATCH 1/4] Precommit tests
---
llvm/test/CodeGen/X86/combine-adc.ll | 49 ++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/llvm/test/CodeGen/X86/combine-adc.ll b/llvm/test/CodeGen/X86/combine-adc.ll
index cb934c8664e45..6c278e7d4a3af 100644
--- a/llvm/test/CodeGen/X86/combine-adc.ll
+++ b/llvm/test/CodeGen/X86/combine-adc.ll
@@ -251,3 +251,52 @@ define i32 @adc_add_multi_use(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, ptr %5) no
declare { i8, i32 } @llvm.x86.addcarry.32(i8, i32, i32)
declare void @use(i8)
+
+define i32 @adc_shl(i32 %a, i32 %b) {
+; X86-LABEL: adc_shl:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: cmpl $70, {{[0-9]+}}(%esp)
+; X86-NEXT: setb %cl
+; X86-NEXT: leal (%ecx,%eax,2), %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: adc_shl:
+; X64: # %bb.0:
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: cmpl $70, %esi
+; X64-NEXT: setb %al
+; X64-NEXT: leal (%rax,%rdi,2), %eax
+; X64-NEXT: retq
+ %add = shl i32 %a, 1
+ %cmp = icmp ult i32 %b, 70
+ %conv = zext i1 %cmp to i32
+ %add1 = or disjoint i32 %add, %conv
+ ret i32 %add1
+}
+
+define i32 @adc_test(i32 %a, i32 %b) {
+; X86-LABEL: adc_test:
+; X86: # %bb.0:
+; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: cmpl $70, {{[0-9]+}}(%esp)
+; X86-NEXT: adcl %eax, %eax
+; X86-NEXT: retl
+;
+; X64-LABEL: adc_test:
+; X64: # %bb.0:
+; X64-NEXT: # kill: def $edi killed $edi def $rdi
+; X64-NEXT: leal (%rdi,%rdi), %ecx
+; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: cmpl $70, %esi
+; X64-NEXT: setb %al
+; X64-NEXT: orl %ecx, %eax
+; X64-NEXT: retq
+ %add = add i32 %a, %a
+ %cmp = icmp ult i32 %b, 70
+ %conv = zext i1 %cmp to i32
+ %add1 = add i32 %add, %conv
+ ret i32 %add1
+}
>From da4f7a1882905e224aa3a93cc93be52363496e6b Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Mon, 24 Aug 2026 09:31:36 -0400
Subject: [PATCH 2/4] [X86] Allow disjoint ors in combineAddOrSubToADCOrSBB
This allows folding to adc or sbb
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 9 ++++++++-
llvm/test/CodeGen/X86/combine-adc.ll | 17 ++++++-----------
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index bf435b0c2f849..cda649be84f4b 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -53627,9 +53627,13 @@ static SDValue combineAddOrSubToADCOrSBB(bool IsSub, const SDLoc &DL, EVT VT,
/// with CMP+{ADC, SBB}.
static SDValue combineAddOrSubToADCOrSBB(SDNode *N, const SDLoc &DL,
SelectionDAG &DAG) {
- bool IsSub = N->getOpcode() == ISD::SUB;
SDValue X = N->getOperand(0);
SDValue Y = N->getOperand(1);
+
+ if (N->getOpcode() == ISD::OR && !N->getFlags().hasDisjoint())
+ return SDValue();
+
+ bool IsSub = N->getOpcode() == ISD::SUB;
EVT VT = N->getValueType(0);
if (SDValue ADCOrSBB = combineAddOrSubToADCOrSBB(IsSub, DL, VT, X, Y, DAG))
@@ -53923,6 +53927,9 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
if (SDValue R = combineOrWithGF2P8AFFINEQB(N, dl, DAG, VT))
return R;
+ if (SDValue R = combineAddOrSubToADCOrSBB(N, dl, DAG))
+ return R;
+
return SDValue();
}
diff --git a/llvm/test/CodeGen/X86/combine-adc.ll b/llvm/test/CodeGen/X86/combine-adc.ll
index 6c278e7d4a3af..e7d0743cdd852 100644
--- a/llvm/test/CodeGen/X86/combine-adc.ll
+++ b/llvm/test/CodeGen/X86/combine-adc.ll
@@ -256,19 +256,17 @@ define i32 @adc_shl(i32 %a, i32 %b) {
; X86-LABEL: adc_shl:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: addl %eax, %eax
; X86-NEXT: cmpl $70, {{[0-9]+}}(%esp)
-; X86-NEXT: setb %cl
-; X86-NEXT: leal (%ecx,%eax,2), %eax
+; X86-NEXT: adcl $0, %eax
; X86-NEXT: retl
;
; X64-LABEL: adc_shl:
; X64: # %bb.0:
; X64-NEXT: # kill: def $edi killed $edi def $rdi
-; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: leal (%rdi,%rdi), %eax
; X64-NEXT: cmpl $70, %esi
-; X64-NEXT: setb %al
-; X64-NEXT: leal (%rax,%rdi,2), %eax
+; X64-NEXT: adcl $0, %eax
; X64-NEXT: retq
%add = shl i32 %a, 1
%cmp = icmp ult i32 %b, 70
@@ -287,12 +285,9 @@ define i32 @adc_test(i32 %a, i32 %b) {
;
; X64-LABEL: adc_test:
; X64: # %bb.0:
-; X64-NEXT: # kill: def $edi killed $edi def $rdi
-; X64-NEXT: leal (%rdi,%rdi), %ecx
-; X64-NEXT: xorl %eax, %eax
+; X64-NEXT: movl %edi, %eax
; X64-NEXT: cmpl $70, %esi
-; X64-NEXT: setb %al
-; X64-NEXT: orl %ecx, %eax
+; X64-NEXT: adcl %edi, %eax
; X64-NEXT: retq
%add = add i32 %a, %a
%cmp = icmp ult i32 %b, 70
>From 960cbd469f85547848798e14cb8821ab97124fc1 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Mon, 24 Aug 2026 10:41:23 -0400
Subject: [PATCH 3/4] Address feedback
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 2 +-
llvm/test/CodeGen/X86/combine-adc.ll | 5 +++--
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index cda649be84f4b..acf7eb562589f 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -53627,13 +53627,13 @@ static SDValue combineAddOrSubToADCOrSBB(bool IsSub, const SDLoc &DL, EVT VT,
/// with CMP+{ADC, SBB}.
static SDValue combineAddOrSubToADCOrSBB(SDNode *N, const SDLoc &DL,
SelectionDAG &DAG) {
+ bool IsSub = N->getOpcode() == ISD::SUB;
SDValue X = N->getOperand(0);
SDValue Y = N->getOperand(1);
if (N->getOpcode() == ISD::OR && !N->getFlags().hasDisjoint())
return SDValue();
- bool IsSub = N->getOpcode() == ISD::SUB;
EVT VT = N->getValueType(0);
if (SDValue ADCOrSBB = combineAddOrSubToADCOrSBB(IsSub, DL, VT, X, Y, DAG))
diff --git a/llvm/test/CodeGen/X86/combine-adc.ll b/llvm/test/CodeGen/X86/combine-adc.ll
index e7d0743cdd852..df20563489bc3 100644
--- a/llvm/test/CodeGen/X86/combine-adc.ll
+++ b/llvm/test/CodeGen/X86/combine-adc.ll
@@ -249,8 +249,6 @@ define i32 @adc_add_multi_use(i32 %0, i32 %1, i32 %2, i32 %3, i32 %4, ptr %5) no
ret i32 %13
}
-declare { i8, i32 } @llvm.x86.addcarry.32(i8, i32, i32)
-declare void @use(i8)
define i32 @adc_shl(i32 %a, i32 %b) {
; X86-LABEL: adc_shl:
@@ -295,3 +293,6 @@ define i32 @adc_test(i32 %a, i32 %b) {
%add1 = add i32 %add, %conv
ret i32 %add1
}
+
+declare { i8, i32 } @llvm.x86.addcarry.32(i8, i32, i32)
+declare void @use(i8)
>From 4e67aac197591a820df31e3d78b8bfe85335427e Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Mon, 24 Aug 2026 13:09:41 -0400
Subject: [PATCH 4/4] Move
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index acf7eb562589f..a0e903d8d317a 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -53630,12 +53630,11 @@ static SDValue combineAddOrSubToADCOrSBB(SDNode *N, const SDLoc &DL,
bool IsSub = N->getOpcode() == ISD::SUB;
SDValue X = N->getOperand(0);
SDValue Y = N->getOperand(1);
+ EVT VT = N->getValueType(0);
if (N->getOpcode() == ISD::OR && !N->getFlags().hasDisjoint())
return SDValue();
- EVT VT = N->getValueType(0);
-
if (SDValue ADCOrSBB = combineAddOrSubToADCOrSBB(IsSub, DL, VT, X, Y, DAG))
return ADCOrSBB;
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