[llvm] [AArch64][SDAG] Enable +sme2p2/+sve2p2 lowering for compressstore (PR #218624)

[Benjamin Maxwell via llvm-commits]

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@@ -334,6 +334,11 @@ class AArch64TTIImpl final : public BasicTTIImplBase<AArch64TTIImpl> {
   }
 
   bool isElementTypeLegalForCompressStore(Type *Ty) const {
+    if ((ST->hasSVE2p2() || ST->hasSME2p2()) &&
+        ((Ty->isIntegerTy(8) || Ty->isIntegerTy(16)) ||
+         ((Ty->isHalfTy() || Ty->isBFloatTy()) &&
+          Ty->getScalarSizeInBits() == 16)))
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MacDue wrote:

Can half/bfloat not have a scalar size of 16-bits?

https://github.com/llvm/llvm-project/pull/218624