[llvm] [AArch64][SDAG] Enable +sme2p2/+sve2p2 lowering for compressstore (PR #218624)

[Benjamin Maxwell via llvm-commits]

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@@ -2303,6 +2303,13 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     }
   }
 
+  if ((Subtarget->isSVEAvailable() && Subtarget->hasSVE2p2()) ||
+      (Subtarget->isSVEorStreamingSVEAvailable() && Subtarget->hasSME2p2())) {
+    // With +sve2p2/+sme2p2 the full range of vector types are supported.
+    for (auto VT : {MVT::nxv16i8, MVT::nxv8i16, MVT::nxv8f16, MVT::nxv8bf16})
+      setOperationAction(ISD::MSTORE, VT, Custom);
+  }
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MacDue wrote:

I think it'd good to move this (and the previous handling for the SVE1 cases) next to where we set the legality for `ISD::VECTOR_COMPRESS` (the the compresstore lowering depends on `VECTOR_COMPRESS`).

https://github.com/llvm/llvm-project/pull/218624