[llvm] 1769f04 - [VPlan] Add test for miscompile due to select VPlan fold (NFC). (#218516)

[via llvm-commits]

Author: Florian Hahn
Date: 2026-08-25T09:22:33+01:00
New Revision: 1769f04c0f38f37e139322e6b822ade8433b179c

URL: https://github.com/llvm/llvm-project/commit/1769f04c0f38f37e139322e6b822ade8433b179c
DIFF: https://github.com/llvm/llvm-project/commit/1769f04c0f38f37e139322e6b822ade8433b179c.diff

LOG: [VPlan] Add test for miscompile due to select VPlan fold (NFC). (#218516)

Added: 
    

Modified: 
    llvm/test/Transforms/LoopVectorize/select-folds.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/LoopVectorize/select-folds.ll b/llvm/test/Transforms/LoopVectorize/select-folds.ll
index 69c98d995968c..98204ab9891bb 100644
--- a/llvm/test/Transforms/LoopVectorize/select-folds.ll
+++ b/llvm/test/Transforms/LoopVectorize/select-folds.ll
@@ -70,9 +70,62 @@ loop:
 exit:
   ret i32 %or
 }
+
+; Test with a select where the condition is also a value operand.
+define void @not_cmp_select_value_operand(ptr noalias %dst, ptr noalias %a, ptr noalias %b, i64 %n) {
+; CHECK-LABEL: define void @not_cmp_select_value_operand(
+; CHECK-SAME: ptr noalias [[DST:%.*]], ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], i64 [[N:%.*]]) {
+; CHECK-NEXT:  [[ENTRY:.*:]]
+; CHECK-NEXT:    br label %[[VECTOR_PH:.*]]
+; CHECK:       [[VECTOR_PH]]:
+; CHECK-NEXT:    br label %[[VECTOR_BODY:.*]]
+; CHECK:       [[VECTOR_BODY]]:
+; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-NEXT:    [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]]
+; CHECK-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4
+; CHECK-NEXT:    [[TMP1:%.*]] = getelementptr inbounds i8, ptr [[B]], i64 [[INDEX]]
+; CHECK-NEXT:    [[WIDE_LOAD1:%.*]] = load <4 x i8>, ptr [[TMP1]], align 1
+; CHECK-NEXT:    [[TMP2:%.*]] = trunc <4 x i8> [[WIDE_LOAD1]] to <4 x i1>
+; CHECK-NEXT:    [[TMP3:%.*]] = icmp sle <4 x i32> [[WIDE_LOAD]], zeroinitializer
+; CHECK-NEXT:    [[TMP4:%.*]] = select <4 x i1> [[TMP3]], <4 x i1> [[TMP3]], <4 x i1> [[TMP2]]
+; CHECK-NEXT:    [[TMP5:%.*]] = zext <4 x i1> [[TMP4]] to <4 x i8>
+; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i8, ptr [[DST]], i64 [[INDEX]]
+; CHECK-NEXT:    store <4 x i8> [[TMP5]], ptr [[TMP6]], align 1
+; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
+; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100
+; CHECK-NEXT:    br i1 [[TMP7]], label %[[SCALAR_PH:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK:       [[SCALAR_PH]]:
+; CHECK-NEXT:    br label %[[LOOP:.*]]
+; CHECK:       [[LOOP]]:
+; CHECK-NEXT:    ret void
+;
+entry:
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+  %gep.a = getelementptr inbounds i32, ptr %a, i64 %iv
+  %va = load i32, ptr %gep.a, align 4
+  %gep.b = getelementptr inbounds i8, ptr %b, i64 %iv
+  %vb8 = load i8, ptr %gep.b, align 1
+  %y = trunc i8 %vb8 to i1
+  %c = icmp sgt i32 %va, 0
+  %sel = select i1 %c, i1 %c, i1 %y
+  %notc = xor i1 %c, true
+  %sel.z = zext i1 %sel to i8
+  %gep.d = getelementptr inbounds i8, ptr %dst, i64 %iv
+  store i8 %sel.z, ptr %gep.d, align 1
+  %iv.next = add nuw nsw i64 %iv, 1
+  %ec = icmp eq i64 %iv.next, 100
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret void
+}
 ;.
 ; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
 ; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
 ; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
 ; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
+; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
 ;.