[llvm] [TableGen] Split large printInstruction() for NVPTX to avoid compiler limits (PR #218530)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/utils/TableGen/AsmWriterEmitter.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/utils/TableGen/AsmWriterEmitter.cpp b/llvm/utils/TableGen/AsmWriterEmitter.cpp
index 819cc7bb9..1cafd27a7 100644
--- a/llvm/utils/TableGen/AsmWriterEmitter.cpp
+++ b/llvm/utils/TableGen/AsmWriterEmitter.cpp
@@ -561,7 +561,8 @@ void AsmWriterEmitter::EmitPrintInstruction(
       };
 
       uint64_t Mask = (1ULL << NumBits) - 1;
-      O << "\n  // Fragment " << i << ": IIFE to reduce printInstruction() size.\n";
+      O << "\n  // Fragment " << i
+        << ": IIFE to reduce printInstruction() size.\n";
       O << "  if (![this](const MCInst *MI, uint64_t Address, "
         << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
         << "raw_ostream &O, uint64_t Bits) -> bool {\n";
@@ -575,10 +576,13 @@ void AsmWriterEmitter::EmitPrintInstruction(
         auto [B0, R0] = processCmd(Commands[0]);
         auto [B1, R1] = processCmd(Commands[1]);
         O << "    if ((Bits >> " << (OpcodeInfoBits - BitsLeft) << ") & "
-          << Mask << ") {\n" << B1;
-        if (!R1) O << "      return true;\n";
+          << Mask << ") {\n"
+          << B1;
+        if (!R1)
+          O << "      return true;\n";
         O << "    } else {\n" << B0;
-        if (!R0) O << "      return true;\n";
+        if (!R0)
+          O << "      return true;\n";
         O << "    }\n";
       } else {
         O << "    switch ((Bits >> " << (OpcodeInfoBits - BitsLeft) << ") & "
@@ -587,7 +591,8 @@ void AsmWriterEmitter::EmitPrintInstruction(
         for (unsigned j = 0; j < Commands.size(); ++j) {
           auto [Body, HasRet] = processCmd(Commands[j]);
           O << "    case " << j << ":\n" << Body;
-          if (!HasRet) O << "      return true;\n";
+          if (!HasRet)
+            O << "      return true;\n";
         }
         O << "    }\n";
       }
@@ -670,8 +675,10 @@ AsmWriterEmitter::EmitOpcodeGroupTable(raw_ostream &O) {
   // AsmString mnemonic prefix is used as a fine-grained fallback.
   auto getGroupKey = [](const AsmWriterInst &AWI) -> std::string {
     const Record *Def = AWI.CGI->TheDef;
-    if (Def->getValueAsBit("IsLoad")) return "loads";
-    if (Def->getValueAsBit("IsStore")) return "stores";
+    if (Def->getValueAsBit("IsLoad"))
+      return "loads";
+    if (Def->getValueAsBit("IsStore"))
+      return "stores";
     auto isSuldSet = [](const BitsInit *B) {
       for (unsigned i = 0; i < B->getNumBits(); ++i)
         if (auto *Bit = dyn_cast<BitInit>(B->getBit(i)); Bit && Bit->getValue())
@@ -683,9 +690,11 @@ AsmWriterEmitter::EmitOpcodeGroupTable(raw_ostream &O) {
         isSuldSet(Def->getValueAsBitsInit("IsSuld")))
       return "texture";
     StringRef S = Def->getValueAsString("AsmString").ltrim(" \t");
-    if (S.empty() || S[0] == '$' || S[0] == '{' || S[0] == '@') return "misc";
+    if (S.empty() || S[0] == '$' || S[0] == '{' || S[0] == '@')
+      return "misc";
     size_t End = S.find_first_of(".${ \t\\");
-    std::string Key = S.substr(0, End == StringRef::npos ? S.size() : End).str();
+    std::string Key =
+        S.substr(0, End == StringRef::npos ? S.size() : End).str();
     return Key.empty() ? "misc" : Key;
   };
 
@@ -701,7 +710,8 @@ AsmWriterEmitter::EmitOpcodeGroupTable(raw_ostream &O) {
 
   // Dispatch table: 0 = not in overflow set, 1..N = group index.
   // uint8_t caps at 254 non-zero groups; assert before silent truncation.
-  assert(Groups.size() < 255 && "Too many opcode groups for uint8_t dispatch table");
+  assert(Groups.size() < 255 &&
+         "Too many opcode groups for uint8_t dispatch table");
   std::vector<uint8_t> Table(NumberedInstructions.size(), 0);
   for (unsigned GIdx = 0; GIdx < Groups.size(); ++GIdx)
     for (const AsmWriterInst &AWI : Groups[GIdx].second)
@@ -731,7 +741,8 @@ void AsmWriterEmitter::EmitOpcodeGroupDispatch(raw_ostream &O,
     << "    switch (OpcGroup) {\n";
   unsigned GIdx = 0;
   for (auto &[Key, Insts] : Groups) {
-    O << "    case " << (++GIdx) << ": [this](const MCInst *MI, uint64_t Address, "
+    O << "    case " << (++GIdx)
+      << ": [this](const MCInst *MI, uint64_t Address, "
       << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "")
       << "raw_ostream &O) {\n"
       << "      switch (MI->getOpcode()) {\n"

``````````

</details>


https://github.com/llvm/llvm-project/pull/218530