[llvm] [AMDGPU] Extend wide VGPR copy expansion to 96-bit copies (PR #214561)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 24 13:51:47 PDT 2026
https://github.com/robertvirany updated https://github.com/llvm/llvm-project/pull/214561
>From 282a7fae67b40aa82c495441be8a93a43edfdda5 Mon Sep 17 00:00:00 2001
From: Robert Virany <robertvirany at gmail.com>
Date: Wed, 5 Aug 2026 15:52:59 -0600
Subject: [PATCH 1/2] [AMDGPU] Precommit 96-bit VGPR copy test
---
llvm/test/CodeGen/AMDGPU/copy-vgpr96.mir | 55 ++++++++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/copy-vgpr96.mir
diff --git a/llvm/test/CodeGen/AMDGPU/copy-vgpr96.mir b/llvm/test/CodeGen/AMDGPU/copy-vgpr96.mir
new file mode 100644
index 0000000000000..5914e79d77ae7
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/copy-vgpr96.mir
@@ -0,0 +1,55 @@
+# RUN: llc -mtriple=amdgpu9.42 -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s
+
+---
+name: copy_vgpr96_nonoverlap
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr4_vgpr5_vgpr6
+
+ ; CHECK-LABEL: name: copy_vgpr96_nonoverlap
+ ; CHECK: liveins: $vgpr4_vgpr5_vgpr6
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $vgpr0_vgpr1 = V_MOV_B64_e32 $vgpr4_vgpr5, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
+ ; CHECK-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr6, implicit $exec, implicit killed $vgpr4_vgpr5_vgpr6
+ ; CHECK-NEXT: S_ENDPGM 0
+ $vgpr0_vgpr1_vgpr2 = COPY killed $vgpr4_vgpr5_vgpr6
+ S_ENDPGM 0
+
+...
+
+---
+name: copy_vgpr96_overlap_forward
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr2_vgpr3_vgpr4
+
+ ; CHECK-LABEL: name: copy_vgpr96_overlap_forward
+ ; CHECK: liveins: $vgpr2_vgpr3_vgpr4
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $vgpr0_vgpr1 = V_MOV_B64_e32 $vgpr2_vgpr3, implicit $exec, implicit $vgpr2_vgpr3_vgpr4
+ ; CHECK-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit $vgpr2_vgpr3_vgpr4
+ ; CHECK-NEXT: S_ENDPGM 0
+ $vgpr0_vgpr1_vgpr2 = COPY killed $vgpr2_vgpr3_vgpr4
+ S_ENDPGM 0
+
+...
+
+---
+name: copy_vgpr96_overlap_backward
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1_vgpr2
+
+ ; CHECK-LABEL: name: copy_vgpr96_overlap_backward
+ ; CHECK: liveins: $vgpr0_vgpr1_vgpr2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: $vgpr4 = V_MOV_B32_e32 $vgpr2, implicit $exec, implicit $vgpr0_vgpr1_vgpr2
+ ; CHECK-NEXT: $vgpr2_vgpr3 = V_MOV_B64_e32 $vgpr0_vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2
+ ; CHECK-NEXT: S_ENDPGM 0
+ $vgpr2_vgpr3_vgpr4 = COPY killed $vgpr0_vgpr1_vgpr2
+ S_ENDPGM 0
+
+...
>From 70e8a43d1f4b2d0985a36c9f587538e876fc35b9 Mon Sep 17 00:00:00 2001
From: Robert Virany <robertvirany at gmail.com>
Date: Thu, 6 Aug 2026 14:06:03 -0600
Subject: [PATCH 2/2] [AMDGPU] Extend wide VGPR copy expansion to 96-bit copies
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 59 +++++++++++++++++--
.../CodeGen/AMDGPU/GlobalISel/flat-scratch.ll | 3 +-
.../AMDGPU/GlobalISel/strict_fma.f32.ll | 4 +-
llvm/test/CodeGen/AMDGPU/copy-vgpr96.mir | 2 +-
llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir | 12 ++--
.../AMDGPU/llvm.amdgcn.cvt.scale.pk.ll | 32 +++++-----
llvm/test/CodeGen/AMDGPU/load-constant-i32.ll | 4 +-
.../AMDGPU/lower-work-group-id-intrinsics.ll | 6 +-
8 files changed, 82 insertions(+), 40 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index b2ae51a1b85f7..7c6a682473419 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -1168,7 +1168,6 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
} else if ((Size % 64 == 0) && RI.hasVGPRs(RC) &&
(RI.isProperlyAlignedRC(*RC) &&
(SrcRC == RC || RI.isSGPRClass(SrcRC)))) {
- // TODO: In 96-bit case, could do a 64-bit mov and then a 32-bit mov.
if (ST.hasVMovB64Inst()) {
Opcode = AMDGPU::V_MOV_B64_e32;
EltSize = 8;
@@ -1178,6 +1177,59 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
}
}
+ // If there is an overlap, we can't kill the super-register on the last
+ // instruction, since it will also kill the components made live by this def.
+ const bool Overlap = RI.regsOverlap(SrcReg, DestReg);
+ const bool CanKillSuperReg = KillSrc && !Overlap;
+
+ if (ST.hasVMovB64Inst() && AMDGPU::VReg_96RegClass.hasSubClassEq(RC) &&
+ (SrcRC == RC || RI.isSGPRClass(SrcRC))) {
+ const TargetRegisterClass *WideRC =
+ getRegClass(get(AMDGPU::V_MOV_B64_e32), /*OpNum=*/1);
+
+ Register DstWideLow = RI.getSubReg(DestReg, AMDGPU::sub0_sub1);
+ Register SrcWideLow = RI.getSubReg(SrcReg, AMDGPU::sub0_sub1);
+
+ const bool DstWideIsLow = WideRC->contains(DstWideLow);
+ const bool SrcWideIsLow = WideRC->contains(SrcWideLow);
+
+ if (DstWideIsLow == SrcWideIsLow) {
+ const unsigned WideSubIdx =
+ DstWideIsLow ? AMDGPU::sub0_sub1 : AMDGPU::sub1_sub2;
+ const unsigned NarrowSubIdx = DstWideIsLow ? AMDGPU::sub2 : AMDGPU::sub0;
+
+ Register WideDst = RI.getSubReg(DestReg, WideSubIdx);
+ Register WideSrc = RI.getSubReg(SrcReg, WideSubIdx);
+ Register NarrowDst = RI.getSubReg(DestReg, NarrowSubIdx);
+ Register NarrowSrc = RI.getSubReg(SrcReg, NarrowSubIdx);
+
+ assert(WideDst && WideSrc && NarrowDst && NarrowSrc &&
+ "Failed to find subregs.");
+
+ const bool WideFirst = Forward == DstWideIsLow;
+
+ const unsigned FirstOpc =
+ WideFirst ? AMDGPU::V_MOV_B64_e32 : AMDGPU::V_MOV_B32_e32;
+ Register FirstDst = WideFirst ? WideDst : NarrowDst;
+ Register FirstSrc = WideFirst ? WideSrc : NarrowSrc;
+
+ const unsigned SecondOpc =
+ WideFirst ? AMDGPU::V_MOV_B32_e32 : AMDGPU::V_MOV_B64_e32;
+ Register SecondDst = WideFirst ? NarrowDst : WideDst;
+ Register SecondSrc = WideFirst ? NarrowSrc : WideSrc;
+
+ BuildMI(MBB, MI, DL, get(FirstOpc), FirstDst)
+ .addReg(FirstSrc)
+ .addReg(SrcReg, RegState::Implicit);
+ BuildMI(MBB, MI, DL, get(SecondOpc), SecondDst)
+ .addReg(SecondSrc)
+ .addReg(SrcReg,
+ getKillRegState(CanKillSuperReg) | RegState::Implicit);
+
+ return;
+ }
+ }
+
// For the cases where we need an intermediate instruction/temporary register
// (destination is an AGPR), we need a scavenger.
//
@@ -1189,11 +1241,6 @@ void SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RC, EltSize);
- // If there is an overlap, we can't kill the super-register on the last
- // instruction, since it will also kill the components made live by this def.
- const bool Overlap = RI.regsOverlap(SrcReg, DestReg);
- const bool CanKillSuperReg = KillSrc && !Overlap;
-
for (unsigned Idx = 0; Idx < SubIndices.size(); ++Idx) {
unsigned SubIdx;
if (Forward)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
index fbdaee61479bf..4abbe961a0105 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
@@ -2811,8 +2811,7 @@ define void @store_load_v3i32_unaligned(ptr addrspace(5) nocapture %arg) {
; GFX942-NEXT: s_mov_b32 s1, 2
; GFX942-NEXT: s_mov_b32 s0, 1
; GFX942-NEXT: v_mov_b32_e32 v4, s2
-; GFX942-NEXT: v_mov_b32_e32 v3, s1
-; GFX942-NEXT: v_mov_b32_e32 v2, s0
+; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX942-NEXT: scratch_store_dwordx3 v0, v[2:4], off sc0 sc1
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: scratch_load_dwordx3 v[0:2], v0, off sc0 sc1
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
index cd2f12548aec6..b330dc056072b 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
@@ -278,8 +278,8 @@ define void @v_constained_fma_v3f32_fpexcept_strict_uni(<3 x float> inreg %x, <3
; GFX942-NEXT: v_pk_fma_f32 v[2:3], s[2:3], v[2:3], v[4:5]
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readfirstlane_b32 s2, v2
-; GFX942-NEXT: v_mov_b32_e32 v3, s1
-; GFX942-NEXT: v_mov_b32_e32 v2, s0
+; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_mov_b32_e32 v4, s2
; GFX942-NEXT: global_store_dwordx3 v[0:1], v[2:4], off
; GFX942-NEXT: s_waitcnt vmcnt(0)
diff --git a/llvm/test/CodeGen/AMDGPU/copy-vgpr96.mir b/llvm/test/CodeGen/AMDGPU/copy-vgpr96.mir
index 5914e79d77ae7..dad49f4bc4674 100644
--- a/llvm/test/CodeGen/AMDGPU/copy-vgpr96.mir
+++ b/llvm/test/CodeGen/AMDGPU/copy-vgpr96.mir
@@ -1,4 +1,4 @@
-# RUN: llc -mtriple=amdgpu9.42 -verify-machineinstrs -run-pass=postrapseudos -o - %s | FileCheck %s
+# RUN: llc -mtriple=amdgpu9.42 -run-pass=postrapseudos -o - %s | FileCheck %s
---
name: copy_vgpr96_nonoverlap
diff --git a/llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir b/llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
index 09cd36fb60e9a..a033247abf3be 100644
--- a/llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
+++ b/llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir
@@ -221,8 +221,7 @@ body: |
; GFX942-LABEL: name: copy_v96_to_v96
; GFX942: liveins: $vgpr4_vgpr5_vgpr6
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
- ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
+ ; GFX942-NEXT: $vgpr0_vgpr1 = V_MOV_B64_e32 $vgpr4_vgpr5, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
; GFX942-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr6, implicit $exec, implicit killed $vgpr4_vgpr5_vgpr6, implicit $exec
;
; GFX10-LABEL: name: copy_v96_to_v96
@@ -235,8 +234,7 @@ body: |
; GFX1250-LABEL: name: copy_v96_to_v96
; GFX1250: liveins: $vgpr4_vgpr5_vgpr6
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr0 = V_MOV_B32_e32 $vgpr4, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
- ; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr5, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
+ ; GFX1250-NEXT: $vgpr0_vgpr1 = V_MOV_B64_e32 $vgpr4_vgpr5, implicit $exec, implicit $vgpr4_vgpr5_vgpr6
; GFX1250-NEXT: $vgpr2 = V_MOV_B32_e32 $vgpr6, implicit $exec, implicit killed $vgpr4_vgpr5_vgpr6, implicit $exec
$vgpr0_vgpr1_vgpr2 = COPY killed $vgpr4_vgpr5_vgpr6, implicit $exec
...
@@ -720,8 +718,7 @@ body: |
; GFX942-LABEL: name: copy_s96_to_v96
; GFX942: liveins: $sgpr0_sgpr1_sgpr2
; GFX942-NEXT: {{ $}}
- ; GFX942-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
- ; GFX942-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
+ ; GFX942-NEXT: $vgpr0_vgpr1 = V_MOV_B64_e32 $sgpr0_sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX942-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2, implicit $exec
;
; GFX10-LABEL: name: copy_s96_to_v96
@@ -734,8 +731,7 @@ body: |
; GFX1250-LABEL: name: copy_s96_to_v96
; GFX1250: liveins: $sgpr0_sgpr1_sgpr2
; GFX1250-NEXT: {{ $}}
- ; GFX1250-NEXT: $vgpr0 = V_MOV_B32_e32 $sgpr0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
- ; GFX1250-NEXT: $vgpr1 = V_MOV_B32_e32 $sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
+ ; GFX1250-NEXT: $vgpr0_vgpr1 = V_MOV_B64_e32 $sgpr0_sgpr1, implicit $exec, implicit $sgpr0_sgpr1_sgpr2
; GFX1250-NEXT: $vgpr2 = V_MOV_B32_e32 $sgpr2, implicit $exec, implicit killed $sgpr0_sgpr1_sgpr2, implicit $exec
$vgpr0_vgpr1_vgpr2 = COPY killed $sgpr0_sgpr1_sgpr2, implicit $exec
...
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
index 712fe047f770d..e80e73d12d9d2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
@@ -592,8 +592,8 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_ss(<3 x i32> inreg %src, i32
; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT: v_nop
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1
-; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v12, s2
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_fp6 v[2:9], v[10:12], s3
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
@@ -642,8 +642,8 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_sl(<3 x i32> inreg %src, ptr
; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT: v_nop
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1
-; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v12, s2
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_fp6 v[2:9], v[10:12], 0x64 scale_sel:1
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
@@ -721,8 +721,8 @@ define amdgpu_ps void @test_cvt_scale_pk16_bf16_fp6_sl(<3 x i32> inreg %src, ptr
; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT: v_nop
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1
-; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v12, s2
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_bf16_fp6 v[2:9], v[10:12], 0x64 scale_sel:3
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
@@ -800,8 +800,8 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_ss(<3 x i32> inreg %src, i32
; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT: v_nop
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1
-; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v12, s2
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_bf6 v[2:9], v[10:12], s3 scale_sel:4
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
@@ -850,8 +850,8 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_sl(<3 x i32> inreg %src, ptr
; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT: v_nop
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1
-; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v12, s2
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_bf6 v[2:9], v[10:12], 0x64 scale_sel:5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
@@ -929,8 +929,8 @@ define amdgpu_ps void @test_cvt_scale_pk16_bf16_bf6_sl(<3 x i32> inreg %src, ptr
; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT: v_nop
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1
-; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v12, s2
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_bf16_bf6 v[2:9], v[10:12], 0x64 scale_sel:8
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
@@ -1014,8 +1014,8 @@ define amdgpu_ps void @test_cvt_scale_pk16_f32_fp6_ss(<3 x i32> inreg %src, i32
; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT: v_nop
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v20, s2 :: v_dual_mov_b32 v19, s1
-; GFX1250-GISEL-NEXT: v_mov_b32_e32 v18, s0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v20, s2
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f32_fp6 v[2:17], v[18:20], s3 scale_sel:5
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
@@ -1112,8 +1112,8 @@ define amdgpu_ps void @test_cvt_scale_pk16_f32_bf6_ss(<3 x i32> inreg %src, i32
; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-GISEL-NEXT: v_nop
; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v20, s2 :: v_dual_mov_b32 v19, s1
-; GFX1250-GISEL-NEXT: v_mov_b32_e32 v18, s0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v20, s2
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f32_bf6 v[2:17], v[18:20], s3 scale_sel:6
; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
index d1c53d2d8641a..665f84001a5f5 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
@@ -306,8 +306,8 @@ define amdgpu_kernel void @constant_load_v3i32(ptr addrspace(1) %out, ptr addrsp
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b96 s[4:6], s[2:3], 0x0 nv
; GFX1250-NEXT: s_wait_kmcnt 0x0
-; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s4
-; GFX1250-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6
+; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s6
+; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[0:1]
; GFX1250-NEXT: s_endpgm
entry:
diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
index a64937abebb41..3ffe9c76175ae 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
@@ -114,7 +114,7 @@ define amdgpu_cs void @_amdgpu_cs_main() {
; GFX1250-GISEL-NEXT: s_add_co_i32 s5, s5, s3
; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s2, 0
; GFX1250-GISEL-NEXT: s_cselect_b32 s2, s4, s5
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX1250-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null
; GFX1250-GISEL-NEXT: s_endpgm
@@ -192,7 +192,7 @@ define amdgpu_cs void @workgroup_id_no_clusters() "amdgpu-cluster-dims"="0,0,0"
; GFX1250-GISEL-NEXT: s_mov_b32 s0, ttmp9
; GFX1250-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff
; GFX1250-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX1250-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null
; GFX1250-GISEL-NEXT: s_endpgm
@@ -285,7 +285,7 @@ define amdgpu_cs void @workgroup_id_optimized() "amdgpu-cluster-dims"="2,3,4" {
; GFX1250-GISEL-NEXT: s_lshl1_add_u32 s0, ttmp9, s0
; GFX1250-GISEL-NEXT: s_add_co_i32 s1, s2, s1
; GFX1250-GISEL-NEXT: s_lshl2_add_u32 s2, s3, s4
-; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s2
; GFX1250-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null
; GFX1250-GISEL-NEXT: s_endpgm
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