[llvm] [AMDGPU] Model ordered XDL writes in expert scheduling (PR #218326)

[via llvm-commits]

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@@ -51,8 +51,9 @@ AMDGPU_HW_EVENT(VGPR_FLAT_READ,             28) /* read VGPR source in FLAT */
 AMDGPU_HW_EVENT(VGPR_VMEM_READ,             29) /* read VGPR source in other VMEM */
 AMDGPU_HW_EVENT(ASYNC_ACCESS,               30) /* access that uses ASYNC_CNT */
 AMDGPU_HW_EVENT(TENSOR_ACCESS,              31) /* access that uses TENSOR_CNT */
+AMDGPU_HW_EVENT(VGPR_XDL_ORDERED_WRITE,     32) /* write VGPR dest in ordered XDL VALU */
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vporpo wrote:

I don't think this should be a separate event. My understanding is that an event is a high-level concept that describes the hardware path that an instruction is being executed in. The fact that a specific instruction provides some in-order counter update guarantee should not be an event-level concept but rather an implementation detail within the logic of the wait insertion pass.

@Pierre-vh any thoughts on this?

https://github.com/llvm/llvm-project/pull/218326