[llvm] [X86] Allow disjoint ors in combineAddOrSubToADCOrSBB (PR #218410)

[Simon Pilgrim via llvm-commits]

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@@ -53639,9 +53627,13 @@ static SDValue combineAddOrSubToADCOrSBB(bool IsSub, const SDLoc &DL, EVT VT,
 /// with CMP+{ADC, SBB}.
 static SDValue combineAddOrSubToADCOrSBB(SDNode *N, const SDLoc &DL,
                                          SelectionDAG &DAG) {
-  bool IsSub = N->getOpcode() == ISD::SUB;
   SDValue X = N->getOperand(0);
   SDValue Y = N->getOperand(1);
+
+  if (N->getOpcode() == ISD::OR && !N->getFlags().hasDisjoint())
+    return SDValue();
+
+  bool IsSub = N->getOpcode() == ISD::SUB;
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RKSimon wrote:

You shouldn't need to move the IsSub/VT lines? Just check for disjoint OR afterward

https://github.com/llvm/llvm-project/pull/218410