[llvm] [X86] Lower bf16->f32/f64 fpext without a GPR round-trip (PR #218359)

[Phoebe Wang via llvm-commits]

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@@ -462,6 +462,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
     setOperationAction(ISD::BF16_TO_FP, VT, Expand);
     setOperationAction(ISD::FP_TO_BF16, VT, Custom);
   }
+  // The vector-based lowering below needs SSE2 registers.
+  if (!Subtarget.useSoftFloat() && Subtarget.hasSSE2()) {
+    setOperationAction(ISD::BF16_TO_FP, MVT::f32, Custom);
+    setOperationAction(ISD::BF16_TO_FP, MVT::f64, Custom);
+  }
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phoebewang wrote:

Move to the existing hasSSE2 block.

https://github.com/llvm/llvm-project/pull/218359