[llvm] [X86] Lower bf16->f32/f64 fpext without a GPR round-trip (PR #218359)

[Simon Pilgrim via llvm-commits]

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@@ -22973,6 +22978,40 @@ static SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) {
   return Res;
 }
 
+SDValue X86TargetLowering::LowerBF16_TO_FP(SDValue Op,
+                                           SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  SDValue Src = Op.getOperand(0);
+  // Operand is usually already softened to i16 by type legalization.
+  if (Src.getValueType() == MVT::bf16)
+    Src = DAG.getBitcast(MVT::i16, Src);
+  else
+    Src = DAG.getAnyExtOrTrunc(Src, DL, MVT::i16);
+
+  // Peek through to bf16's underlying f16 register
+  MVT VecVT = MVT::v8i16;
+  SDValue VecSrc = Src;
+  if (Src.getOpcode() == ISD::BITCAST &&
+      Src.getOperand(0).getValueType() == MVT::f16) {
+    VecSrc = Src.getOperand(0);
+    VecVT = MVT::v8f16;
+  }
+
+  // Shift the bf16 bits into the high half of the f32.
+  SDValue Vec = DAG.getBitcast(
+      MVT::v8i16, DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VecVT, VecSrc));
+  Vec = DAG.getBitcast(MVT::v4i32, Vec);
+  Vec = getTargetVShiftByConstNode(X86ISD::VSHLI, DL, MVT::v4i32, Vec, 16, DAG);
+  Vec = DAG.getBitcast(MVT::v4f32, Vec);
+  SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Vec,
----------------
RKSimon wrote:

DAG.getExtractVectorElt

https://github.com/llvm/llvm-project/pull/218359